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https://designers-guide.org/forum/YaBB.pl Simulators >> RF Simulators >> simulating phase modulation with PAC https://designers-guide.org/forum/YaBB.pl?num=1199890595 Message started by fedora on Jan 9th, 2008, 6:56am |
Title: simulating phase modulation with PAC Post by fedora on Jan 9th, 2008, 6:56am I attempt to simulate phase modulation with the PSS and PAC analysis. The circuit is shown in the attachment. Since the amplitude of the inverter output is limited by the supply voltage, I think the PAC result contains only PM contents at the vout node. When the inverter in the fig is a transistor level module, the simulation is sucessful. While I replace it with a verilogA module, the PAC magnitude is 0 at the vout node. How can I write a verilogA invertor which can reponse the PAC correctly. The netlist is as following: simulator lang=spectre global 0 include "/tools/ic5141/tools/dfII/samples/artist/ahdlLib/quantity.spectre" parameters fref=100M INV (vin vout) not_gate vlogic_high=0.6 vlogic_low=-0.6 vtrans=0 tdel=0 \ trise=100p tfall=100p V1 (vin 0) vsource dc=0 type=pulse delay=0 val0=-600.0m val1=600.0m \ period=1/fref rise=100p fall=100p width=0.5/fref-200p pacmag=1 \ fundname="VPULSE" pss pss fund=100M harms=100 errpreset=moderate tstab=12n pac pac sweeptype=relative relharmnum=1 start=100 stop=20M + dec=10 maxsideband=5 annotate=status freqaxis=absout ahdl_include "inv.va" The file inv.va is as following: `include "discipline.h" `include "constants.h" module not_gate(vin, vout); input vin; output vout; electrical vin, vout; parameter real vlogic_high = 5; parameter real vlogic_low = 0; parameter real vtrans = 1.4; parameter real tdel = 2u from [0:inf); parameter real trise = 1u from (0:inf); parameter real tfall = 1u from (0:inf); real vout_val; integer logic_in; analog begin logic_in = V(vin) > vtrans; @ (cross(V(vin) - vtrans, 1)) logic_in = 1; @ (cross(V(vin) - vtrans, -1)) logic_in = 0; vout_val = !(logic_in) ? vlogic_high : vlogic_low; V(vout) <+ transition( vout_val, tdel, trise, tfall); end endmodule |
Title: Re: simulating phase modulation with PAC Post by Frank Wiedmann on Jan 9th, 2008, 7:55am See http://www.designers-guide.org/Forum/YaBB.pl?num=1189658426/4#4 (and the link given there). |
Title: Re: simulating phase modulation with PAC Post by Ken Kundert on Jan 9th, 2008, 11:36am Frank's post suggests that the problem you are having is that the limiter you are using abruptly switches, and so cannot pass the small signal. You would be better served using a limiter that has finite gain in the transition region. That is relatively easy to do with a limiter, but then you will see some small amount of AM at the output of the limiter. Alternatively, you can use the PM modulator given at www.verilog-ams.com. -Ken |
Title: Re: simulating phase modulation with PAC Post by fedora on Jan 9th, 2008, 10:08pm Frank Wiedmann wrote on Jan 9th, 2008, 7:55am:
Thank you and Ken. I am in fact simulating a PLL and the link is what I want. |
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