The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design Languages >> Verilog-AMS >> convergence problem
https://designers-guide.org/forum/YaBB.pl?num=1200252009

Message started by priya on Jan 13^th, 2008, 11:20am

Title: convergence problem
Post by priya on Jan 13^th, 2008, 11:20am

Dear Friends,
First of all my thanks to the wonderful site,so informative and helpful.

I have modeled a double gate MOSFET using verilog-a(on mentor graphics ADvance MS tool).Its running properly and showing me the expected characteristics of the device.Then I used the model developed to design an inverter(on ELDO),and it does not simulate.It shows convergence error.When I run the code,it starts DC ramping and then the system hangs.
Please help and suggest.
Thanks.

Title: Re: convergence problem
Post by rajdeep on Jan 15^th, 2008, 2:04am

Hi,

It is hard to comment without seeing the code.

So I wud make one general comment on this.

Make sure that the interface of the MOS model is electrical in nature.
By electrical I mean all the interfaces should have some finite impedance.
Only writing say "electrical out" is not suffiecient. Convergence issues can arise
if say two voltage sources are in parallel or two current sources are connected
to one node without any finite impedance connected to that node.

Don't know how much will it help..

Rajdeep

Title: Re: convergence problem
Post by Geoffrey_Coram on Jan 16^th, 2008, 7:41am

I agree with Rajdeep: hard to say without seeing the code.

Did you read my tutorials from BMAS 2004:
http://www.bmas-conf.org/2004/papers/bmas04-coram.pdf
http://www.bmas-conf.org/2004/presentations/bmas04-coram-preso.pdf

There are a number of poor modeling techniques that might work fine in a digital or mixed-signal tool, but that don't really make sense in an analog simulator.

Title: Re: convergence problem
Post by rajdeep on Jan 17^th, 2008, 7:12am

Hi Geoffrey,

I found the paper quite useful and in some cases it reminded me of the mistakes I have done while coding with VerilogA. But I could not understand the example that illustrates bad usage of if statement.

Quote:

if (vbs == 0.0) begin
qbs = 0.0;
capbs = czbs+czbssw+czbsswg;
end else if (vbs < 0.0) begin
qbs = …
…
I(b,s) <+ ddt(qbs);

Quote:

Resulting C code:
if (vbs == 0.0) {
qbs = 0.0;
dqbs_dvbs = 0.0;
//capbs=czbs+czbssw+czbsswg;
} else if (vbs < 0.0) {
qbs = …
…

I have pasted the two slides I could not understand well. What is the relation between dqbs_dvbs and the next line ( shown commented)??

Rajdeep

Title: Re: convergence problem
Post by Geoffrey_Coram on Jan 28^th, 2008, 6:58am

rajdeep wrote on Jan 17^th, 2008, 7:12am:

Hi Geoffrey,
I have pasted the two slides I could not understand well. What is the relation between dqbs_dvbs and the next line ( shown commented)??

dqbs_dvbs is what the simulator computes as the derivative of qbs; the next line is what the model-writer wanted.

In C, the model-writer knows that, when vbs==0, q=0 and there's no need to do all the calculations. However, in Verilog-A, if you try to skip the calculations, you end up with the wrong derivative!

Title: Re: convergence problem
Post by rajdeep on Jan 31^st, 2008, 11:04pm

Does this mean we should not assign the derivative of a variable dependent on node voltage
or current by ourselves in verilogA?
bcoz the C code generated by the 'model-writer' (a compiler???) ignores
that line and computes its own derivative.

Plz confirm!

Thanks!
Rajdeep

Title: Re: convergence problem
Post by Geoffrey_Coram on Feb 4^th, 2008, 5:21am

rajdeep wrote on Jan 31^st, 2008, 11:04pm:

That's right, the Verilog-A compiler computes all the derivatives that the simulator needs, based on the potential or flow (voltage or current) contributions (<+) in the model.

Title: Re: convergence problem
Post by NKS on Feb 12^th, 2008, 1:03am

Geoffrey_Coram wrote on Feb 4^th, 2008, 5:21am:

rajdeep wrote on Jan 31^st, 2008, 11:04pm:

That's right, the Verilog-A compiler computes all the derivatives that the simulator needs, based on the potential or flow (voltage or current) contributions (<+) in the model.

Hello Geoffrey,

I didn't quite catch your response to rajdeep's question about ending up with the wrong derivative if you skip a calculation in Verilog-A. :-[ Where did you skip the calculation in your bad usage example? Or rather, I think it would be more helpful if you could post the proper/correct coding for the bad usage example. What would a proper Verilog-A code look like in the example mentioned?

Thanks in advance,

NKS

Title: Re: convergence problem
Post by Geoffrey_Coram on Feb 22^nd, 2008, 6:54am

The original C code had something like
if (vbs == 0.0) {
qbs = 0.0;
cbs = czero_bs;
} else ...

You should *NEVER* have a == test involving a voltage-dependent quantity (vbs) in Verilog-A, because you'll end up lying about the derivatives.

The Verilog-A code should be
if (vbs <= 0) begin
qbs =
end else begin
qbs =
end

that is, only 2 branches, and there's no cbs calculation, because Verilog-A computes the derivatives automatically. You of course need to be sure that qbs(vbs=0-) = qbs(vbs=0+), but the original model developer did that for you in this case.