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Design >> RF Design >> QVCO mismatch
https://designers-guide.org/forum/YaBB.pl?num=1200286473

Message started by yhq0413 on Jan 13^th, 2008, 8:54pm

Title: QVCO mismatch
Post by yhq0413 on Jan 13^th, 2008, 8:54pm

I am designing a 4G QVCO.
The phase error is simulated with PSS.
schematic simulation result shows 0 90.1 180.3 270.5
then the simulation is performed on extracted layout netlist that includes the parasitic resistance and capacitance,the result shows 0 90 185 275
how can I modify the layout?

Title: Re: QVCO mismatch
Post by neoflash on Jan 19^th, 2008, 7:00am

From schematic level simulation, you should not see any mismatch. You can increase settling time delay setting.

From layout level simulation, I still suggest use transient to see the results. Then judge your next move.