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Design >> Mixed-Signal Design >> SC feedforward SD example - summing stage coeffs
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Message started by thechopper on Jan 14^th, 2008, 12:00pm

Title: SC feedforward SD example - summing stage coeffs
Post by thechopper on Jan 14^th, 2008, 12:00pm

hi All,

If you happen to have access to Schreier's sigma delta book "Understanding Delta-Sigma data converters" (IEEE Press) you might be able to help me out. In Chapter 9 there are several practical examples. In particular the first example corresponds to a fifth-order single-bit noise shaping loop(switched cap feed-forward topology).

The way the design process is described is pretty clear. However, there is a quick question I have concerning the summing stage (prior to the comparator) this example shows. On page 305, a summary tables shows the coefficients and capacitor ratios used in the design for this modulator. Most of these ratios (summing coefficients) are higher than one for the summing stage. However, as it can be seen on the corresponding behavioral schematic on page 309, the summing stage is a passive one. So, how can the design implement higher than one cap ratios with a passive summing stage? Am I missing something?

Many thanks
Tosei

Title: Re: SC feedforward SD example - summing stage coef
Post by bananawolf on Jan 18^th, 2008, 3:59pm

The gain loss of the passive summation can be merged into the single-bit quantizer.
Remember that the single-bit quantizer only detects its ac input signal polarity.
Hope this answers your question.

Title: Re: SC feedforward SD example - summing stage coef
Post by thechopper on Jan 18^th, 2008, 6:50pm

Hi,

That´s make total sense. I guess then the approach shown in the book is only valid for single bit quantizers. Otherwise such gain loss could not be absorbed by the quantizer.

Thank for your help
Tosei

Title: Re: SC feedforward SD example - summing stage coef
Post by panditabupesh on Mar 4^th, 2008, 6:56pm

For a multibit quantizer the 'vref' could be divided by the passive capacitor loss. Silva did that in in his thesis, but it seems as it reduces the LSB size, was not happy with the results.

Bupesh

Title: Re: SC feedforward SD example - summing stage coef
Post by thechopper on Mar 5^th, 2008, 5:51pm

I guess that for a multi-bit approach where coefficients are still less than 1, a passive approach might be an option. Certainly it is not in case there are coefficients higher than 1.

Tosei

Title: Re: SC feedforward SD example - summing stage coef
Post by panditabupesh on Mar 6^th, 2008, 4:40am

Suppose, you want to implement coefficients 2,3, and 4. You could use capacitors of sizes 2, 3, and 4. The effective coefficients you are getting will be 2/9, 3/9 and 4/9. Now to compensate for the 1/9 factor you divide the quantizer reference range by 9. Dividing reference range is equivalent to having a gain-stage before the quantizer.

Am I missing something about coefficients greater than unity?

Bupesh