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Simulators >> Circuit Simulators >> Simulation time point??
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Message started by rajdeep on Jan 15^th, 2008, 2:14am

Title: Simulation time point??
Post by rajdeep on Jan 15^th, 2008, 2:14am

Hi all,

Is the following statement true considering a spice like simulator (Cadenc spectre actually)

If I add a 1us clock source using an ideal voltage source in a design, which is pretty fast (takes say around
200us of time step without the clock source) the simulation time step becomes smaller and cannot go above
1us. This is because of the clock source.

Rajdeep

Title: Re: Simulation time point??
Post by Stefan on Jan 15^th, 2008, 2:28am

The highest frequency in the solver's matrix defines the time steps (if well above the accuracy criteria).
Your statement is true.

But if you just want to reduce the simulation time step... there's an simulator option for max_timestep...

Title: Re: Simulation time point??
Post by rajdeep on Jan 15^th, 2008, 3:53am

Hi stefan,

No no I do not want to increase my simulation speed up in this way, rather I have to add a clock and I find the simulation time is increasing due to this. This was expected!! But what I could not understand that the simulator takes steps greater than 1us!! How is it possible if I have a clock continously ticking at 1us, and not only that (possibly due to this) when I plot the clock waveform it is not showing a perfect 1us clock!!! rather at many places...like the following...
[img][/img]

As you can see after sometime the clock waveform is wrong. Infact the simualtion time step suddenly starts to become more. The clock was generated by using an ideal pulse type voltage source from analogLib.

Rajdeep

Title: Re: Simulation time point??
Post by rajdeep on Jan 15^th, 2008, 9:15am

Well, I just came to know that one has to specify the max step!! otherwise spectre can miss simulation
points. That came as a surprise :-?

Title: Re: Simulation time point??
Post by John O Donovan on Jan 15^th, 2008, 10:00am

Rajdeep,

This is surprising and not the correct behavior. What version of Spectre are you using ? Can you reproduce the problem in a simple netlist ?

Thanks,
John

Title: Re: Simulation time point??
Post by rajdeep on Jan 15^th, 2008, 9:25pm

The version is this.
sub-version 5.10.41.110605

Well, I just added 1K resistance across the pulse generator and the problem got solved!!!!!
The other and more deterministic way is to force the max_step = 500ns (1/2 T of clk).

By the way I'm using spectreVerilog simulator..

Rajdeep

Title: Re: Simulation time point??
Post by Ken Kundert on Jan 17^th, 2008, 12:31am

Generally this occurs when there is a very large voltage else where in the circuit, perhaps because of of some idealized behavioral models in the circuit. Try setting the transient option relref to alllocal.

-Ken