The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl Simulators >> AMS Simulators >> problem encountered during elaboration https://designers-guide.org/forum/YaBB.pl?num=1200410305 Message started by aaronhor on Jan 15th, 2008, 7:18am |
Title: problem encountered during elaboration Post by aaronhor on Jan 15th, 2008, 7:18am Hi, I have encountered problem to elaborate my project. To start with, I have 3 VHDL blocks in my project, namely DPWM,PID_compensator, and ADC. i have successfully connected DPWM and PID_compensator together and compile, elaborate them without any errors. So I assume both of the blocks are ok and ready to simulate. The problem arise in the ADC block. I think the problem arise because I use VHDL in describing it rather than verilog-ams or vhdl-ams. The following error message appears: ncelab: *E,CFMPTC (../hc/zzz_adc/schematic/verilog.vams,17|51): VHDL port ADC_DELAY_CELL_3.OUTPUT (../hc/adc_delay_cell_3/entity/vhdl.vhd: line 10, position 16) type is not compatible with Verilog. the correspong VHDL port is : Port ( vdd : in real range 0.0 to 5.0; input : in STD_LOGIC; reset : in STD_LOGIC; output : out STD_LOGIC); the error message point out that the output port is incompatible with verilog. But I wonder is it due to input port vdd ? Does type real supported in this case? the connect module I use is copied from the one used in quick start tutorial. I just copy the whole connect lib module over and use it. the connect rule I use is ConnRule_25V_mid. Thanks a lot |
Title: Re: problem encountered during elaboration Post by aaronhor on Jan 17th, 2008, 6:25am Hi , I face another problem in elaboration. This time is due to my model files. Error found by spectre. "/net/wildar/software2/local/library/CSM/chrt018IC_DK010_Rev1B/018IC_3P3V/models/YI-093- SM011/sm093011-1c.scs" 103: Illegal library definition found in netlist ncelab: *F,SPRSER: Spice/Spectre file parsing failed. I do include the analog models "/net/wildar/software2/local/library/CSM/chrt018IC_DK010_Rev1B/018IC_3P3V/models/YI-093-SM011/sm093011-1c.scs" and section name "typical". in the hierarchy editor. in the cds.lib file. I also got define the library chrt018IC DEFINE chrt018IC /net/wildar/software2/local/library/CSM/chrt018IC_DK010_Rev1B/018IC_3P3V/chrt018IC I also can run simulation using ADE tools but face this problem once I use ams. Please help. Thanks a lot Regards, Aaronhor |
The Designer's Guide Community Forum » Powered by YaBB 2.2.2! YaBB © 2000-2008. All Rights Reserved. |