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Design >> Analog Design >> maximum possible Gm/Id for a transistor
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Message started by vivkr on Jan 15^th, 2008, 7:30am

Title: maximum possible Gm/Id for a transistor
Post by vivkr on Jan 15^th, 2008, 7:30am

We know that the gm/Id of a BJT is (1/Vt) where Vt = (kT/q) and at 300 K, (gm/Id) ~ 38.
This gm/Id is independent of whether the BJT is PNP or NPN, made of Si, Ge or anything else.

We also know that the gm/Id of a MOS transistor is always less than the gm/Id for a BJT. At
best, this can come within 0.8x - 0.9x of the BJT value, when the MOS transistor is in weak inversion.
The above limitation cannot be surpassed for any given transistor.

My question: Is it possible in any way using circuit techniques to enhance the effective gm/Id of
a transistor-based amplifier? If yes, then how? Naturally, if one were applying methods to
boost effective gm, then Id is replaced by total current consumed by any blocks used in the process.
I am wondering if positive feedback could be brought into play somehow.

Thanks & Regards
Vivek

Title: Re: maximum possible Gm/Id for a transistor
Post by thechopper on Jan 21^st, 2008, 11:33am

Hi Vivek,

Certainly positive feedback (as a known mean for boosting gain) can be used to improve the gm of a gain stage. The way I know applies to a differential pair,
Typically, a degen resistor is used as a negative feedback means for better setting the gm of a common source stage. The same obvioulsy can be extended to a diff pair
with degeneration. Now, what if the degen resistor is negative. You end up getting a boosted (rahter than reduced) composite gm. This can be easily achieved
by replacing the passive degen resistor by a gate cross-coupled mos pair. The impedance of a gate cross-coupled pair is -2/gm. This is now your degen resistor, which
when factored in the composite GM you'll see that boosts it (GM (composite)= gm*K/(1-K); where K is the ratio of the input gm over the degen gm, K <1).
This method does not take extra bais current, therefore gm/ID gets increased.

Hope this helps
tosei

Title: Re: maximum possible Gm/Id for a transistor
Post by didac on Jan 22^nd, 2008, 1:12am

Hi,
I remember looking a presentation of Pavia University where they indicated that due to the increase of speed of PMOS transistors it's not crazy to use a complementary input stage(like a digital inverter) in the low frequency regime, this way for a fixed ID you obtain a global gm of the cell gm=gmp+gmn, the problems wents to an area increase(two transistors and the PMOS must be bigger).
Hope it helps,

Title: Re: maximum possible Gm/Id for a transistor
Post by vivkr on Jan 25^th, 2008, 1:30am

Hi Tosei, didac,

Thanks for the interesting responses. I had forgotten about this +ve feedback idea. I would do it slightly differently though
from what Tosei suggests as I think that method would require use of a larger gm for the boost device than the main device and
result in polarities opposite to conventional ones (not such a big problem). I think making gm,boost slightly smaller in
magnitude to gm,main is good.

The idea of using PMOS and NMOS together is also quite good. I can imagine that it could be particularly useful with newer
technologies or lower supplies.

Thanks both of you.
Vivek