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Design Languages >> Verilog-AMS >> Using Verilog for PLL Closed Loop Sim
https://designers-guide.org/forum/YaBB.pl?num=1200615658

Message started by tm123 on Jan 17^th, 2008, 4:20pm

Title: Using Verilog for PLL Closed Loop Sim
Post by tm123 on Jan 17^th, 2008, 4:20pm

Hello,

I am interested in using Verilog to model some blocks in a PLL in order to do a closed loop PLL simulation. I am interested in the PLL settling, in particular the effect of cycle slipping. I would like to use Verilog to model the VCO and frequency divider. I plan on using the transistor level PFD, CP and loop filter. My questions are:

-Can a simulation be done in Spectre using the Analog Environment with transistor level schematics and Verilog code?
-Is Verilog AMS the best tool to use, or are Verilog-A/VHDL more appropriate for the VCO/frequency divider respectively?
-Does the Verilog code need to be imported into Cadence? If so, how is that done?
-Is there existing documentation or papers that explain this type of simulation?

Thanks for your time.

Regards,
Tim

Title: Re: Using Verilog for PLL Closed Loop Sim
Post by Stefan on Jan 18^th, 2008, 12:28am

-Can a simulation be done in Spectre using the Analog Environment with transistor level schematics and Verilog code?

Only with VerilogA, which would be uninteresting in terms of simulation speed.

-Is Verilog AMS the best tool to use, or are Verilog-A/VHDL more appropriate for the VCO/frequency divider respectively?

VerilogAMS is very well suited for that type of simulation.

-Does the Verilog code need to be imported into Cadence? If so, how is that done?

Use the Library Manager to add a verilog view to the corresponding symbols and use the hierarchy editor to switch between the views for simulation.

-Is there existing documentation or papers that explain this type of simulation?

Yes. Check designers-guide or cadence documentation.

Regards,

Stefan

Title: Re: Using Verilog for PLL Closed Loop Sim
Post by tm123 on Jan 18^th, 2008, 8:45am

Hello Stefan,

Thank you for replying, your answers help a lot. One follow up question:

-Do I need to select the AMS plug-in in the hierarchy editor in order to simulate with Verilog AMS code?

Thanks again.

Tim