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Design >> Mixed-Signal Design >> quesiton about a JSSCC paper (Dr. Maneatis' )
https://designers-guide.org/forum/YaBB.pl?num=1200889467

Message started by keikei on Jan 20^th, 2008, 8:24pm

Title: quesiton about a JSSCC paper (Dr. Maneatis' )
Post by keikei on Jan 20^th, 2008, 8:24pm

I had a question about Dr. Maneatis' paper "Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques" published in JSSCC 1996.
According to Fig.2, the bias voltages VBP and VBN are generated from the control voltage VCTRL. As VCTRL increases, VBP increases and VBN drops.
I think the VCO oscillating frequency should lower when VCTRL increases, Since VBN is used to bias the tail current sources in the buffer stages.
However Fig. 10 shows that the VCO runs faster when VCTRL increases.

Can anyone tell me what the problem is?

Title: Re: quesiton about a JSSCC paper (Dr. Maneatis' )
Post by jeffyan on Jan 21^st, 2008, 3:13am

keikei wrote on Jan 20^th, 2008, 8:24pm:

hi
actually, VCTRL is refer to vdd, so VCTRL= vdd- VCTRL'

Title: Re: quesiton about a JSSCC paper (Dr. Maneatis' )
Post by loose-electron on Jan 22^nd, 2008, 3:10pm

I know that one pretty well - All good architecture except for the charge pump(in my opinion) and it needs a voltage regulator over the VCO for better jitter performance.

As for the positive vs negative voltage coefficient on the VCO controller, whats the big deal? You can do either, as long as you get the polarity reversal elsewhere in the control system.