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Design >> Analog Design >> Any concern of overlap for VIA1 and contact
https://designers-guide.org/forum/YaBB.pl?num=1201157209

Message started by dandelion on Jan 23^rd, 2008, 10:46pm

Title: Any concern of overlap for VIA1 and contact
Post by dandelion on Jan 23^rd, 2008, 10:46pm

Hi,
In my design, with the area considerations, I need the overlaping of via1 and contact, I cehcked the design rule, it gives no infotmation on it. And I also communicated with the foundry, they seemed also not sure about it.

The process is 0.35um 1P4M 18V CMOS.

Would u give me some advcie?

Thanks in advance

Title: Re: Any concern of overlap for VIA1 and contact
Post by ywguo on Jan 24^th, 2008, 3:35am

Hi,

The vias and contact are alowed to be stacked one by one.

Yawei