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Design >> High-Speed I/O Design >> Baud Rate ADC for SerDes, adequate?
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Message started by neoflash on Jan 26^th, 2008, 3:46am

Title: Baud Rate ADC for SerDes, adequate?
Post by neoflash on Jan 26^th, 2008, 3:46am

TI published a paper on 12.5G SerDes with baud rate ADC. My question is that 1x sampling rate will have aliasing and minimum sampling rate should be 2x data rate. How could baud rate ADC achieve clock data recovery?

Title: Re: Baud Rate ADC for SerDes, adequate?
Post by didac on Jan 27^th, 2008, 7:45am

Hi,
If the paper is:"A 12.5Gb/s SerDes in 65nm CMOS Using a Baud-Rate ADC with Digital Receiver Equalization and
Clock Recovery", the title says all:they do the synchronization with DSP, look at the reference [5]:K. Mueller, M. Muller “Timing Recovery in Digital Synchronous DataReceivers” IEEE Trans. on Communications, pp. 516-531, May, 1976. This kind of algorithm if I remember correctly it's based in adaptative convergence, the speed of convergence usually is dependant if you use NDA(Non-Data Aided),DA(Data Aided-->syncronization data sent with the signal and known) or DD(Decision Directed, it decides what symbol it received and adjust following this decision and so on).
Hope it helps,