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Measurements >> Phase Noise and Jitter Measurements >> Is it able to Simulate jitter by verilog-HDL?
https://designers-guide.org/forum/YaBB.pl?num=1201424042

Message started by win3y on Jan 27^th, 2008, 12:54am

Title: Is it able to Simulate jitter by verilog-HDL?
Post by win3y on Jan 27^th, 2008, 12:54am

Is there anyone who can tell me know about simulation jitter by verilog-HDL (Model Sim 5.7)?
I found some papers mentioned this but all are verilog-AMS.
Any comments are wellcome! Thank you very much!!!

Title: Re: Is it able to Simulate jitter by verilog-HDL?
Post by Stefan on Jan 27^th, 2008, 2:16am

verilog misses some extensions (like wreal data-types) that would be crucial for jitter simulations.
However you can implement an oscillator with jitter using $dist_normal (don't know exactly if this is available in pure verilog).

Title: Re: Is it able to Simulate jitter by verilog-HDL?
Post by win3y on Jan 27^th, 2008, 6:29am

Stefan wrote on Jan 27^th, 2008, 2:16am:

Thank you very much for your reply. Now I am sure that $dist_normal is the syntax in verilog-A, not in pure verilog.
Could you tell me know whether can simulate jitter by verilog-A or not? And how can I download software that helps to simulate like Model Sim? Because I'd like to simulate following code.
Thank you very much
Here is code that I found:
// Fixed frequency oscillator with white accumulating jitter.
//
// Accumulating jitter is the jitter associated with a free-running oscillator.
//

module osc2 (out);

output out; voltage out; // output signal
parameter real freq=1 from (0:inf); // output frequency
parameter real vl=-1; // high output voltage
parameter real vh=1; // low output voltage
parameter real tt=0.01/freq from (0:inf); // transition time of output
parameter real jitter=0 from [0:0.1/freq); // white period jitter
integer n, seed;
real next, dT;

analog begin
@(initial_step) begin
seed = 286;
next = 0.5/freq + $abstime;
end
@(timer(next)) begin
n = !n;
dT = jitter*$rdist_normal(seed,0,1);
next = next + 0.5/freq + `M_SQRT1_2*dT;
end
V(out) <+ transition(n ? vh : vl, 0, tt);
end
endmodule

Title: Re: Is it able to Simulate jitter by verilog-HDL?
Post by Stefan on Jan 27^th, 2008, 11:59am

"found Code" *g*

That code is from one of Ken's or Cheng's Papers from this site.

$dist_normal IS pure digital verilog, $rdist_normal is analog behavior.

Software commonly used is either Mentor with eldo or Cadence with spectre.
Since these are commercial tools you won't be able to download them from anywhere.

I don't know if there's a good freeware software available for verilog-A simulations, sorry.

Regards,

Stefan

Title: Re: Is it able to Simulate jitter by verilog-HDL?
Post by win3y on Jan 27^th, 2008, 10:27pm

Stefan wrote on Jan 27^th, 2008, 11:59am:

Dear Stefan,
I am really appreciate your help. To be frank with you, I'd like to tell you my problem.
I need to have two clocks, one includes jitter and then feed them to one D type flip-flop for sampling with hoping to obtain random bits out.
And my problem is how to simulate this module by Model Sim. In other words, how to simulate this clock input that includes jitter?
Could you give me some advices to help me out?

Title: Re: Is it able to Simulate jitter by verilog-HDL?
Post by ywguo on Feb 4^th, 2008, 11:45pm

Hi win3y,

Oh, that is a jittered-oscillator based random number generator. It is interesting. Why do you simulate it with verilog-A? Matlab/C is more suitable if run a behavioral simulation. SPICE/spectre simulation is required for a transistor level simulation.

Good luck
Yawei

Title: Re: Is it able to Simulate jitter by verilog-HDL?
Post by Stefan on Feb 5^th, 2008, 12:33am

System Verification or Mixed Signal / Mixed Domain Simulations with partly transistor based schematics.