The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design >> Mixed-Signal Design >> cascade PLL with low loop bandwidth
https://designers-guide.org/forum/YaBB.pl?num=1201584369

Message started by nowicq on Jan 28^th, 2008, 9:26pm

Title: cascade PLL with low loop bandwidth
Post by nowicq on Jan 28^th, 2008, 9:26pm

I designed PLL, and I want to cascade this PLL.

The first one's feature is as follows:
ref_clock = 54MHz, PLL output clock = 25.2/...../135MHz (8-phases)

and the second one's feature is as follows:
ref_clock = 25.2/.../135MHz, PLL output clock = same as ref_clock (8-phases)
the second PLL's purpose is to adjust phase using 8-phases.

the first one and second one are same PLLs except ref_/feedback_divide ratio.

you know, the second one is used such as DLL.
I know it is good to use DLL but the second one can be used the first one.
So I can't use DLL. ( and there is no more area to include DLL)

Is there any problem in that?

as you know, to get the various PLL output frequency, I use 7-bit divider so loop bandwidth is very low.(about 40KHz)

I simulated using verilog-A model, but I could not get a definite answer.

I need some advice.

Title: Re: cascade PLL with low loop bandwidth
Post by joel on Jan 29^th, 2008, 12:40pm

In practice, I've repeatedly found that cascaded-pll systems work better if the 2nd pll has a higher loop
bandwidth. In my situation, both plls are roots of clock-domains, and data needs to be moved from
the first pll's clock-domain to the 2nd. So the 2nd pll needs to track the 1st pll's 'medium-term' jitter.
I think if you're not moving data from the 1st pll's clock domain to the 2nd pll's clock domain, you could
get lower jitter by lowering the 2nd pll's loop-bandwidth.

I ended up having to add a circuit that detected excessive misalignment between the 1st and 2nd pll's clocks,
which could result in loss of synchronous data transfer between the domains. This would then generate an interrupt,
warning the system of data loss. Alternatively, you could put in fifos, at the expense of area & complexity.

You would do well to put some loop-bandwith tuning parameters under register control. Like doubling both the M, N,
or adjusting the charge-pump current (if its a charge-pump pll). Just some system thoughts for you. Good luck!

Title: Re: cascade PLL with low loop bandwidth
Post by nowicq on Jan 29^th, 2008, 9:25pm

Dear joel,

I don't know exact meaning of data transfer. Do you mean 'CDR'?

Designed PLL is not a CDR. but data is tranfered with clock.

I have one more question about this,

If 5 PLLs are cascaded and the loop bandwidth is 40KHz-1MHz-40KHz-1MHz-40KHz, then is there any problem?

Regards.

Title: Re: cascade PLL with low loop bandwidth
Post by joel on Jan 30^th, 2008, 3:01pm

I just meant this:

pll1 produces a clock1 that clocks a register-bank-1 (RB1)
pll2 produces a clock2 that clocks a register-bank-2 (RB2)

@(posedge clock2) if (enable==1) RB2 = RB1;

So clock1 and clock2 must be plesiochronous, love that word! CDR is a different story.
I've never cascaded 5 plls, but I'd worry about the stages where you've got a 1MHz-bandwidth
pll driving a 40KHz-bandwidth pll. In this case, the clock from the 1MHz-bandwidth PLL might
be able to jitter quite far from the 40KHz-bandwidth pll's output clock. After all, the 40KHz-bandwidth
pll is set up to reject high-frequency phase noise on its input clock.

I hope someone smart pitches in with some theory to analyze this, and maybe a strategy for simulation.

Title: Re: cascade PLL with low loop bandwidth
Post by loose-electron on Feb 26^th, 2008, 6:34pm

simpler is genrally better, and often smaller, especially when you start adding hardware in for filters and all the real estate used there.

Why not come up with an architecture that uses a single loop??? Generate the highest frequency you need in the system, including all the delta phase stuff and generate your clocks from that with some logic???

What you are describing sounds more like stacking Jello cubes on top of each other.

Title: Re: cascade PLL with low loop bandwidth
Post by ywguo on Mar 5^th, 2008, 9:43pm

Hi nowicq,

Why NOT a DLL to generate 8 phases, then select one? I don't understand why you need 5 cascade PLL's.

If you cascade 5 PLL's, the jitter accumulates more and more, especially in the loop bandwidth.

Best regards,
Yawei

Title: Re: cascade PLL with low loop bandwidth
Post by nowicq on Mar 14^th, 2008, 12:21am

Hi Yawei ,

DLL can NOT replace PLL, because PLL should be used for frequency synthesize.
I think it is good to add DLL, but I don't have enough space.
there is just one PLL in chip.
Cascading PLLs mean cascading chips.

I know that jitter is accumulated at the loop bandwidth, so I will use different loop bandwidth for cascading PLLs.
then, I think that jitter will not be accumulated.
how do you think about this?

Best regards,
nowicq