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Design >> Mixed-Signal Design >> dsm two non-overlap clock generator
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Message started by min on Jan 29^th, 2008, 1:37am

Title: dsm two non-overlap clock generator
Post by min on Jan 29^th, 2008, 1:37am

Hi,
I am doing a system design of a 2 order dsm . and I am thinking of the two non-overlap clock generator.what should I be concerned about in designing this part. Is there any paper about this part designing? Any help will be appreciated.

regards,
Min

Title: Re: dsm two non-overlap clock generator
Post by fonseca.ha on Feb 16^th, 2008, 4:07am

Hi
What is DSM? Is it digital state machine?
you can make non overlaping clocks using an SR latch made of two crosscoupled NOR gates, and driving it, at the input with CLOCK and CLOCK inverted.
there sould be some delay in the cross couple.
Does this solve your problem?

Regards,
Humberto

Title: Re: dsm two non-overlap clock generator
Post by min on Feb 17^th, 2008, 7:13pm

Hi Humberto
Thanks for your reply.
I am designing a 3rd cascade stage switch capacitor dsm.I am curious about how to determine

1. ph1 and ph2 non-overlapping time
2. ph1(ph2) and ph1d(ph2d) delay time

the sdm ota clock is 12.5MHz,
can you give me some suggestion?

regards,
Min

Title: Re: dsm two non-overlap clock generator
Post by Berti on Feb 17^th, 2008, 10:39pm

Hi,

the non-overlap time should not be to large because you want as much time for settling as possible. But on the other hand it
should be large enough that the clocks never overlap (taking into account jitter, skew rise-fall time mismatch etc.). An overlapping
clock will destroy the performance.

But since 12.5MHz is relatively slow, I think you can choose a reasonably high non-overlap time (e.g. 0.5ns, this but also depends on you technology, and
rise-fall times of clocks).

Circuit implementation for non-overlapping clock generators you can find in a textbook about DSM (e.g. Schreier)

Good luck, regards

Title: Re: dsm two non-overlap clock generator
Post by Ken Kundert on Feb 18^th, 2008, 12:25am

I believe DSM in this thread refers to ΔΣ modulator.

-Ken

Title: Re: dsm two non-overlap clock generator
Post by safwatonline on Feb 18^th, 2008, 11:34am

How about multi (i.e. >2) non-overlap clocks how to generate them?

Title: Re: dsm two non-overlap clock generator
Post by thechopper on Feb 19^th, 2008, 6:56am

Hi,

"In the CMOS Mixed-Signal Circuit Desing" book from R.J.Bakker, page 377 you have an example of a three phase non-ov ck which can be extended to N phases.
A more crude way is just to use a high freq oscillator and divide its frequency as necessary so that, by means of simple combinational logic you can select the time slot that will correspond to your clock signals. These obviously will not overlap between each other since are derived from a frequency divider. The drawback is that the min non-overlapping time is fixed and equal to the master oscillator period.

Tosei