The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Simulators >> RF Simulators >> digital gate phase noise sensitivity to duty cycle
https://designers-guide.org/forum/YaBB.pl?num=1201654647

Message started by borisk on Jan 29^th, 2008, 4:57pm

Title: digital gate phase noise sensitivity to duty cycle
Post by borisk on Jan 29^th, 2008, 4:57pm

All,

when simulating the output phase noise added by a digital gate, I see a strong dependence on the clock duty cycle. Is this expected behavior?

For instance, if the input to a digital gate is 50%-50% duty cycle the output phase noise is low, whereas it goes up by 20dB or more for a 1/60%-59/60% duty cycle.

I can explain this by the fact that the input spectrum changes as the duty cycle changes, i.e., (with decreasing pulse width, the amplitude of the fundamental will decrease),
thus in terms of an SNR it would appear the be worse --> higher phase noise.

This however doesn't intuitively make sense when one is only concerned with edges (freq/jitter between successive edges). Also, if viewed as sampling noise, then the convolution
of baseband noise by a lower signal amplitude should yield the same phase noise as noise also should get scaled in amplitude.

Any ideas?

Title: Re: digital gate phase noise sensitivity to duty c
Post by Frank Wiedmann on Jan 29^th, 2008, 11:37pm

Normal, time-averaged phase noise results can be difficult to interpret when one is really interested in jitter. I always use the pnoise analysis with "Noise Type: jitter" in such cases.

Title: Re: digital gate phase noise sensitivity to duty c
Post by borisk on Jan 30^th, 2008, 8:55am

Frank,

point taken, but I do need the phase noise as I'm really looking for the PFD phase noise that I need for the PLL linear noise model.

What I noticed in the pnoise form is that noise type can be set to sources/jitter/modulated... My initial results were with type=sources.

When I set it to modulated and look at the PM component, the overall result is better - more like what I expect. I am not sure whether this is really what I need because I come from HSPICE RF/ELDO RF land, so I'm ramping up on Spectre RF particulars.

If any ideas, please fire away!

Thanks,

Boris

Title: Re: digital gate phase noise sensitivity to duty c
Post by Frank Wiedmann on Jan 30^th, 2008, 11:07pm

Well, if it's really jitter you are trying to model with the "PFD phase noise", you could also simulate with "Noise Type: jitter" and convert time to phase by multiplying with 2πf. For details about strobed or timedomain noise, please see http://www.designers-guide.org/Analysis/sc-filters.pdf. Pnoise jitter analysis is a special case of pnoise timedomain analysis, where you specify the timepoint by giving a threshold value for the signal.

Title: Re: digital gate phase noise sensitivity to duty c
Post by borisk on Jan 31^st, 2008, 11:37am

Thanks Frank. I'll take a look at that.