The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Simulators >> AMS Simulators >> verilog(rtl) code for phase frequency detector
https://designers-guide.org/forum/YaBB.pl?num=1202390493

Message started by nikki on Feb 7^th, 2008, 5:21am

Title: verilog(rtl) code for phase frequency detector
Post by nikki on Feb 7^th, 2008, 5:21am

:-[ can any one please help me wid d verilog coding of phase frequency detector in pll?

Title: Re: verilog(rtl) code for phase frequency detector
Post by sheldon on Feb 8^th, 2008, 3:08am

Nikki,

Any reason to implement the PFD in RTL? Wouldn't it be easier to do
at the gate level? You should be able to implement a gate level version
directly from most block diagrams/schematics.

Best Regards,

Sheldon

Title: Re: verilog(rtl) code for phase frequency detector
Post by nikki on Feb 8^th, 2008, 4:20am

yes it would be easy to do the top level simulation but for a documentation purpose the requirement is as such i implement it using rtl code.

rtl code for pfd and divider both

if u cud help....