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Modeling >> Semiconductor Devices >> MOS-capacitance of NMOS/PMOS
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Message started by Berti on Feb 19^th, 2008, 7:57am

Title: MOS-capacitance of NMOS/PMOS
Post by Berti on Feb 19^th, 2008, 7:57am

Hi all,

I recently simulated a MOS capacitor. This is shown in the Figure for NMOS and PMOS, when sweeping
the voltage over the capacitor. However, I observed that the maximum capacitance in inversion is different
for NMOS and PMOS (PMOS on the left side, NMOS on the right side of the plot).

To me it is not clear why this is the case.
Does anybode have an explanation for that?

Regars

Title: Re: MOS-capacitance of NMOS/PMOS
Post by vivkr on Feb 19^th, 2008, 11:08pm

Hi Berti

Could you post a snapshot of your setup?

Vivek

Title: Re: MOS-capacitance of NMOS/PMOS
Post by Berti on Feb 19^th, 2008, 11:59pm

Sure, the voltage source is sweeped from -vdd to +vdd and the capacitance measured accordingly.
I also replaced the NMOS by a PMOS. Therefore inversion happens for -vin for PMOS and +vin for NMOS,
considering the figure from the first post.

Title: Re: MOS-capacitance of NMOS/PMOS
Post by Geoffrey_Coram on Feb 22^nd, 2008, 6:43am

I would think the poly gate and substrate doping levels are going to be different. Particularly on the poly gate, there's a poly depletion effect that could change the effective "d" in the eps A / d formula for capacitance.

Title: Re: MOS-capacitance of NMOS/PMOS
Post by Berti on Feb 24^th, 2008, 10:13pm

Thanx Geoffrey, sounds reasonable.

Title: Re: MOS-capacitance of NMOS/PMOS
Post by vivkr on Feb 25^th, 2008, 2:59am

Geoffrey_Coram wrote on Feb 22^nd, 2008, 6:43am:

Hi Geoffrey,

Would this also lead to the "buried channel" effect in 1/f noise? The channel must be significantly below the surface
to cause a visible change in "d". I would imagine that 1/f noise drops a lot. What do you think?

Berti: Does your PMOS have much less noise in output current for a given DC current at a given size compared to the NMOS?

Regards
Vivek

Title: Re: MOS-capacitance of NMOS/PMOS
Post by Geoffrey_Coram on Feb 25^th, 2008, 4:34am

vivkr wrote on Feb 25^th, 2008, 2:59am:

Would this also lead to the "buried channel" effect in 1/f noise? The channel must be significantly below the surface
to cause a visible change in "d". I would imagine that 1/f noise drops a lot. What do you think?

I have heard that PMOS devices have lower 1/f because of the buried channel. Probably the peak concentration of the NWELL channel implant for the PMOS is below the surface (I don't have a sense for how far), whereas the NMOS channel is the P substrate and is evenly spread (except for pocket implants?).

Title: Re: MOS-capacitance of NMOS/PMOS
Post by Berti on Feb 25^th, 2008, 6:41am

Hi Vivek,

NMOS and PMOS show very similar flicker-noise. That's also agrees to measurement
results from publications about 1/f-noise using a 130nm technolgy.

Regards