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Design >> RF Design >> PSRR of PLL
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Message started by jimwest on Feb 22^nd, 2008, 12:10am

Title: PSRR of PLL
Post by jimwest on Feb 22^nd, 2008, 12:10am

Hi folks,
I am stucked in simulating the PSRR of PLL.
The pss+pxf might be useful, but is it possible to get the transfer function in the lock state?
And I was told there is a way to get the PSRR of the PLL with the VCO voltage and current load requirement.
I want the details of this method.

Thanx alot!

Jim

Title: Re: PSRR of PLL
Post by Ken Kundert on Feb 22^nd, 2008, 12:55am

Figure out how long it takes to go into lock, set tstab to a value at least that, and run a PSS analysis. You will now have the periodic operating point of the PLL in lock. Then run PXF. The transfer function from Vdd to the output is the small-signal coupling from the supply to the output in terms of voltage. If you are interested in the output in terms of jitter or phase noise, you will have to use one of the more advanced forms of PXF that allows you to define the output in terms of the timing of the signal crossings.

-Ken

Title: Re: PSRR of PLL
Post by jimwest on Feb 24^th, 2008, 6:05pm

Hi Ken,
I got it. Thanx alot!
One more question, is the more advanced forms of PXF, you mentioned, an option or a new feature of the latest version of spectre?

Kindest Regards,

Jim

Title: Re: PSRR of PLL
Post by Frank Wiedmann on Feb 24^th, 2008, 11:30pm

Sampled PXF analysis was introduced in MMSIM6.0 USR1. As far as I can tell, it seems to work correctly. On the other hand, sampled PAC analysis, which was introduced in the same release, is still rather buggy. CCR 417613 has been filed for this, it is currently in the Checked_In state.

Title: Re: PSRR of PLL
Post by loose-electron on Feb 26^th, 2008, 6:11pm

And, while you are at it, put an internal voltage regulator in over the VCO if it is a ring oscillator PLL in a mixed signal environment, keep the VCO differential (duh!) and locally decouple and isolate the VCO system.

Its not simulation issues but all of the above are generally needed.

- Jerry

Title: Re: PSRR of PLL
Post by scsiu on Mar 26^th, 2008, 2:36am

Hi everybody,

I am also simulating PSR of PLL, but I face a problem on the simulation.

I simulate PSR by adding sinusoid wave on VDD and FFT the transient output. But the transient output have a AM modulation due to VDD(i.e. when the output of cmos buffer is logic high, the output would be VDD), and it masked the phase noise due to VDD noise. Should I chop the AM noise out before taking measurement?

Thanks
Marco