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Design >> RF Design >> Impact of PLL frequency divide ratio
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Message started by sandman on Feb 25^th, 2008, 5:06am

Title: Impact of PLL frequency divide ratio
Post by sandman on Feb 25^th, 2008, 5:06am

Hi,

I'm a newbie in PLL design and was wondering if someone could help me with the following queries.

From the divider of the integer divide by N in the feedback loop of the PLL;

1) How does the frequency divide ratio affect phase noise and settling time ?
2) Does the divide ratio affect the bandwidth or any other parameters in the PLL ?
3) Would there be equations where I could confirm these relation ?

If anyone's aware of resources where I could find this information, that would also be much appreciated.

Any help would be appreciated ! Thanks in advance.

Cheers.

Title: Re: Impact of PLL frequency divide ratio
Post by tm123 on Feb 26^th, 2008, 9:32am

Hello Sandman,

-You can think of the divide ratio as the closed loop gain from the input reference phase (input to phase/frequency detector) to the output phase (VCO output in most cases). This effects the PLL in-band phase noise, to which the contributors are the PFD/CP, N divider, reference divider, basically everything except the VCO and loop filter resistor. Therefore, a lower N value will give lower in-band phase noise. The tradeoff of higher/lower reference frequency should also be evaluated when chosing the desired N value.
-The PLL loop filter components should be calculated for a given N value, along with Kd, Kvco, desired phase margin, and desired bandwidth. A larger N value will yield lower capacitor values and higher resistor values with all else being the same, which would increase the phase noise contribution from the resistor itself.
-Equations can be found in many basic PLL papers. A good basic PLL document is PLL Performance, Simulation, and Design by Dean Banerjee, which I think can be downloaded for free from the National Semiconductor website.

Hope this helps.

Tim

Title: Re: Impact of PLL frequency divide ratio
Post by loose-electron on Feb 26^th, 2008, 5:43pm

The textbooks by Gardner, Best and Wolaver all cover this stuff pretty well. It is control systems theory at the first order.

Performance in jitter, and loop damping (smaller zeta) degrade with a higher divide ratio.

Get the equations out of a PLL book, and plug it into a Excel spread sheet, or a simulator, and you can see how they interact.

Title: Re: Impact of PLL frequency divide ratio
Post by sandman on Feb 27^th, 2008, 4:00am

Hello Tim and loose-electron,

Thanks for your inputs. I really appreciate it.

Cheers.

Title: Re: Impact of PLL frequency divide ratio
Post by khouly on Mar 24^th, 2008, 6:57am

the divide ratio N , will increase the phase noise coming from the reference oscillator by 20log(N)

khouly