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Modeling >> Semiconductor Devices >> MOS cap in accumulation region in N-well process
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Message started by vivkr on Feb 27^th, 2008, 3:02am

Title: MOS cap in accumulation region in N-well process
Post by vivkr on Feb 27^th, 2008, 3:02am

Hi,

I am using a PMOS as a cap in accumulation region. The substrate is insulating and the cap is in an NWELL.
Normally, capacitance in accumulation region is Cox, and I imagine that high frequencies ought not to be a problem
BUT is this correct? Does the capacitance stay at Cox for higher frequencies as well. I have a long and wide channel.

Is there something I need to look out for? Linearity is not critical for my application, the caps are only used in a voltage
doubler. I have some well parasitics modelled in my setup, but would appreciate some inputs about potential risks
of MOS cap operation in accumulation vs. inversion.

Thanks
Vivek

Title: Re: MOS cap in accumulation region in N-well proce
Post by Berti on Feb 28^th, 2008, 4:05am

Hi Vivek,

I think the disadvantage of accumulation-mode MOS-capacitors is the high ESR, which is usually
not modelled in the transistor model. This might be a problem for high frequencies.

Regards

Title: Re: MOS cap in accumulation region in N-well proce
Post by imd1 on Feb 28^th, 2008, 4:25am

I think that the PMOS in an n-well is exactly the structure used to implement high-quality varactors in RF VCOs...
The capacitance goes from Cox (at accumulation) to Cox in series with Cchannel (in inversion), about 2X to 3X change, I think.
The only difference between this MOSCAP and the PMOS is the fact that the p+ implants (S/D) are not done, there are n+ implants instead, whcih are used to contact the bulk as close as possible to minimize the loss (resistive drop).

The Spice model used for these are the same as for the PMOS (BSIM3vx), but having different parameters.

If you do a careful layout (minimize gate resistance and bulk resistance) a PMOS should work OK as decoupling cap, I think.