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Design Languages >> Verilog-AMS >> Voltage value assignment to a real variable
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Message started by egarcia on Feb 28^th, 2008, 10:10am

Title: Voltage value assignment to a real variable
Post by egarcia on Feb 28^th, 2008, 10:10am

Hi,

I'm new in verilog-ams and I'm trying to reuse a system verilog tetsbench for my mixed-signal validation environment and there is a small issue I would like to address:

I'm able to read an analog value and assign it to a real variable in verilog-D using something called "XMR" function in synopsys discovery tool. By doing this, I'm able to create a checker using my system verilog stuff and it's working fine. However, this method is tool dependent and I would like to use a more general approach for any other tool (such as mentor ADMS). How can I assign a voltage value to a real signal?

I tried to access an analog net in verilog-d like this, which is not working and I'm not surprised about it :) :

real_variable = top_level.digital_wrapper_1.digital_wrapper2.spice_netlist.net;

So then I created a vams module in order to do the above instruction (this is just one of my approaches but none of them worked):

`include "disciplines.vams"

module spy();
wreal spy_signal;

analog begin
spy_signal = top_level.digital_wrapper_1.digital_wrapper2.spice_netlist.net;
end
endmodule

The idea is to access the spy_signal from the system verilog testbench but I got compilation errors, and since I'm really newbie I don't know what's the solution.

So, any suggestions of what can I do?

Thanks

Title: Re: Voltage value assignment to a real variable
Post by Stefan on Feb 29^th, 2008, 12:48am

I think I remember something like this :

// declare internal node, look for inherited connections for correct syntax
(* node=/toplevel.... *)

// then you could do
assign real_output = V(node);

Regards,

Stefan