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Modeling >> Semiconductor Devices >> extracting substrate parasitics
https://designers-guide.org/forum/YaBB.pl?num=1205325678

Message started by vivkr on Mar 12^th, 2008, 5:41am

Title: extracting substrate parasitics
Post by vivkr on Mar 12^th, 2008, 5:41am

I am wondering if there is a good method to extract substrate parasitics (parasitic BJTs, diodes) from a layout.
I do not have AssuraRF suite but I believe that it does not extract devices either but only passives.

I would like to do this extraction by hand for a very small but sensitive circuit. I have some understanding
of which parasitic devices to expect between wells but am not clear of the impact of substrate and well contacts.

Is there any reference available somewhere that might be of help?

Thanks
Vivek

Title: Re: extracting substrate parasitics
Post by Ken Kundert on Mar 12^th, 2008, 9:52am

Take a look at A Substrate Modeling Methodology (http://www.designers-guide.org/Modeling/substrate-coupling.pdf).

-Ken

Title: Re: extracting substrate parasitics
Post by vivkr on Mar 13^th, 2008, 12:07am

Thanks !!!

Vivek