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Design >> Analog Design >> an active-RC integrator
https://designers-guide.org/forum/YaBB.pl?num=1206586245

Message started by analoghua on Mar 26^th, 2008, 7:50pm

Title: an active-RC integrator
Post by analoghua on Mar 26^th, 2008, 7:50pm

We had designed an folded-cascode opamp with two stages of amplification. The folded-cascode stage has a gain of about 47dB and the second common-source stage has a gain of about 15dB. From AC analysis, the 3dB bandwidth is about 120kHz, the unit-gain frequency is about 200Mhz and the phase margin is about 70 degrees. Transient analysis shows that the slew rate is about 100V/us. However, when using the amplifier to form an active-RC integrator, the transient response for integration looks very poor in terms of the settling to the steady-state output? This is shown in the attached picture. The differential input shown in blue is a 0.2V 2.3MHz sinwave, the output of the integrator shown in red, settles very slowly. Can anyone tell what is wrong with the amplifer or the integrator to have such kind of behavior? Something wrong with the common-mode feedback? By the way, the low-frequency gain of the overall opamp-RC integrator is 65dB, larger than the gain of the opamp itself, whereas the 3dB bandwidth of the integrator is 1.7kHz, which seems very small, and 2.3MHz is the frequency at which the integrator gain is 0dB. Thank you for the help.