The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl Modeling >> Semiconductor Devices >> Doubling length in pseudo cascodes https://designers-guide.org/forum/YaBB.pl?num=1207112421 Message started by thechopper on Apr 1st, 2008, 10:00pm |
Title: Doubling length in pseudo cascodes Post by thechopper on Apr 1st, 2008, 10:00pm Hi All, I have a simple question that usually makes me doubt and for which I got different answers: In current steering DACs or any other structure comprising MOS current mirrors if doubling the length of the unit cell is required a pseudo cascode (the pseudo cascode involves two MOS in series with their gates tied together to the same potential) is usually the option. The question is: where should the bulk of the cascode device be connected to in order to get an effective length of 2L (L is the length of the both devices) , to its own source or to the source of the main current mirror? I'm interested in your comments. Best Regards Tosei |
Title: Re: Doubling length in pseudo cascodes Post by vivkr on May 30th, 2008, 4:20am Hi Tosei, I would tie it to the bulk of the main current mirror. By the way, the name "pseudo-cascode" is confusing. After all, you are simply extending the length of the transistor by adding another element in series, just as you would use multiple elements in series with gates and bulks shorted if you wanted to make an extremely long and narrow transistor, say 1/1000. Regards Vivek |
Title: Re: Doubling length in pseudo cascodes Post by thechopper on Jun 23rd, 2008, 6:17pm Hi Vivek, By tying the bulk of the cascode guy to the main one's bulk the problem is the body effect: if you work out the math assuming the main mirror is in triode mode while the cascode one is in saturation you find that the output current vs the input current ratio is not 1/2, assuming you are just trying to double the length. From this one would think the bulk of the cascode one should be connected to its own source. I see you could tweak the length of the cascode device to get exactly 1/2 of the reference current in the case of sharing the bulk connection so, which one is the more appropriate way? Regards Tosei |
Title: Re: Doubling length in pseudo cascodes Post by vivkr on Jun 23rd, 2008, 11:02pm Hi Tosei, Leaving out the math for the moment, I would say that a current ratio of 2:1 is anyway not achieved that easily if the lengths are scaled as 1:2. This is because the simple, scalable, square-law model is anyway not applicable to most cases, unless you are using extremely long channel devices. So you would need to do some tweaking regardless of the method you use. You would need to check but I think that the impact of body effect in the cascode transistor ought to be minimal. A larger VT also means that the drain voltage (for an NMOS mirror) can be lower than the gate by a larger amount before the transistor leaves the saturation region, to give a long-channel analogy. However, you will need to check with the particular mirror design you are using. In any case, the supply rejection of the mirror will be better when both devices share the same bulk node as the Gmb of the cascode will kick in to enhance the gain due to the cascode. Regards Vivek |
Title: Re: Doubling length in pseudo cascodes Post by thechopper on Jun 24th, 2008, 7:27pm Hi Vivek, Thanks for your answer. I found an old discussion about this topic here http://www.designers-guide.org/Forum/YaBB.pl?num=1162979112 where you got involved. Bottom line from this discussion was that the bulks should be together and the bulk effect should get canceled out by some non-obvious term, which I understand might be what you are referring to with the square-law model not being totally applicable. I agree with the supply rejection being better with both bulks being together. However, I was not able to find any discussion concerning the case of having both bulks tied to their own source voltage. Again simple model equations (source-referred) predict same Vth for both devices under this condition and therefore exactly half current with respect to 1X device. At the same time I agree with the description you posted in the discussion I referred to above, concerning the way of treating the channel of one device as comprised by N segments with only the last one being under pinch off. I find hard to conciliate both approaches though. Regards Tosei |
Title: Re: Doubling length in pseudo cascodes Post by vivkr on Jun 24th, 2008, 11:02pm Hi Tosei, Good that you found the old link. I was going to post it myself. I almost forgot while writing the last post that you are speaking of "pseudo-cascodes" where both gates are tied together. Some of my previous post to you here is thus incorrect or irrelevant. I think you must have figured out from the previous old discussions that you basically have only 1 transistor when you connect 2 in series and have the same gate and bulk. So, there is really no need to worry about body effect as it is not relevant. When we speak of body effect, we are speaking of the source end of the channel and the V(G,S) needed to create inversion there, but in your "pseudo-cascode" connection, that source end is the lower transistor, which anyway has its source and bulk tied together. The "channel" of the pseudo-cascode extends from the source of the lower device to the drain of the higher one. I don't quite understand what you mean when you speak of the difficulty in conciliating both approaches. Perhaps you can explain. Regards Vivek |
Title: Re: Doubling length in pseudo cascodes Post by thechopper on Jun 25th, 2008, 8:27pm vivkr wrote on Jun 24th, 2008, 11:02pm:
Hi Vivek, What I meant is that I still do not see clearly the differences between: A) Tying the both bulks together B) Tying each bulk to the corresponding device´s source According to source referred models (BSIM) in case A) the body effect should play a role in the device under saturation mode, since there would be a difference between its bulk and its own source voltages. Therefore Iout should not be exactly 1/2*Iref (I agree with your description of considering the actual source the one for the lower device and therefore body effect does not play a role, but I understand source referred models are not following such assumption) For case B) source referred model predicts an output current of exactly 1/2*Iref since body effect on the upper device is eliminated (this is not true if we base the description of the problem based on considering the two devices as only one). So, are we talking here about incompatible models (source referred vs body referred?) I would expect both models give the same results. It is highly likely I might be interpreting something wrong though. Thanks and regards Tosei |
Title: Re: Doubling length in pseudo cascodes Post by vivkr on Jun 26th, 2008, 3:07am Hi Tosei, (A) Tying both bulks together This reduces the 2 devices to 1 single transistor. Thus, you have a reference transistor with current I, and ratio (W/L) vs. a mirror transistor with length(W/2*L). This will give a ratio of 2:1. I don't see why this would not be the case provided you use relatively large devices to get around short-channel effects. (B) Tying source-bulk together for top transistor This changes the situation. I would say that you will not get 2:1 current ratio. Maybe you can run a simple simulation to see for yourself. A good test would be to do a DC sweep on the reference current and see which mirror gives a more faithful 2:1 ratio. I bet it would be (A). Regards Vivek |
Title: Re: Doubling length in pseudo cascodes Post by thechopper on Jun 26th, 2008, 7:36pm Hi Vivek, If you base the analysis in a source referred model I would say results are opposed to what you stated. In both A) and B) we will have that For the bottom transistor (1) ID=Β(VG-Vth1)×Vd1-1/2×Vd1^2 (Q1 triode) , while For the top transistor (2) ID=Β/2(VG-Vd1-Vth2)^2 (Q2 saturation) Now, based on this model, in case A) Vth1 ≠ Vth2 due to body effect, while in case B) Vth1=Vth2. Equating both currents and solving such equation for case B you will get ID=Β/4(VG-Vth2)^2, which means ID=1/2×IREF. Therefore the two devices in series with the bulk tied to their respective sources look like exactly a 2L device. Where do you think the error is in this derivation? Thanks Tosei |
Title: Re: Doubling length in pseudo cascodes Post by vivkr on Jun 26th, 2008, 11:25pm Hi Tosei, I cannot offer you an equation-based explanation. It is too dangerous, since the assumptions used may not hold. Let me try another explanation: (A) will clearly have a current ratio of 2:1 if you are able to neglect short-channel effects (have long enough channels) and channel-length modulation, because essentially you have just 1 transistor. (B) This is not the same scenario as (A). If A has 2:1 and this is different, then it cannot possibly be 2:1. When you write the equations, you assume that one transistor is in saturation or linear region. I find this problematic, because you cannot really know this a priori, nor can you know the drain voltage Vd1 a priori (which amounts to the same thing). Just to show that this assumption of regions of operation is problematic, let me outline 2 scenarios: (A) You cannot directly assume that transistor 1 is in linear region and transistor 2 in saturation. If Vd2 is large enough in relation to Vg-Vt, you may have no channel at all in transistor 2 and there may even be pinchoff in transistor 1. Conduction still occurs. After all, it also occurs despite pinchoff at the drain end in a transistor. (B) Since bulk-source are tied together in transistor 2, this has a higher (Vgs-Vt). It is conceivable that neither transistor is in saturation when you do this. If you really want to make a reality check, try running some sims with a LEVEL 0 SPICE model of a MOSFET where you can really get square-law behavior and other distractions are missing. I rest my case. Regards Vivek |
Title: Re: Doubling length in pseudo cascodes Post by thechopper on Jun 27th, 2008, 7:38pm Hi Vivek, I basically agree with your description, except for the last comment on the case (B): if bulk and source are tied together, then VGS is the minimum possible for such W/L, as opposed when bulk has a lower voltage than the source (NMOS case) where VGS-VT is higher. I´ll try to see if I can run some simulations for comparison purposes. Thanks for this helpful discussion. Regards Tosei |
The Designer's Guide Community Forum » Powered by YaBB 2.2.2! YaBB © 2000-2008. All Rights Reserved. |