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https://designers-guide.org/forum/YaBB.pl Design >> Analog Design >> Design of Rail-Rail OTA in 45nm Process https://designers-guide.org/forum/YaBB.pl?num=1207147200 Message started by neoflash on Apr 2nd, 2008, 7:39am |
Title: Design of Rail-Rail OTA in 45nm Process Post by neoflash on Apr 2nd, 2008, 7:39am It finally comes. Process scaling is so aggressive that designing a simple op-amp becomes so hard. In 45nm process, Vth of transistor is as high as 450mV-500mV while the voltage supply is as low as 0.95v. Any good idea to design a rail-rail OTA in this kind of process? |
Title: Re: Design of Rail-Rail OTA in 45nm Process Post by Berti on Apr 3rd, 2008, 12:36am Hi Neoflash, I also encountered the problem of high vt at low supply. I think multi-stage (e.g. nested-miller) amplifiers are a very good option for continuous-time circuits. Of course, the design is more complex than for a single-stage OTA, but you can achieve high gain and bandwidth without the need for stacking more the 3 devices (take a look at the paper from G.Mitteregger from ISSCC 2006). For discrete-time (switched-capacitor) I haven't found a good solution, yet. I am just interested: Does the technology your are using also offer low-vt or even analog process options (which are not available for you)? Regards |
Title: Re: Design of Rail-Rail OTA in 45nm Process Post by neoflash on Apr 3rd, 2008, 7:09am Actually there is low-vt device, however, the threshold voltage is just 20-30mv lower than normal Vt device. |
Title: Re: Design of Rail-Rail OTA in 45nm Process Post by ACWWong on Apr 4th, 2008, 5:42am You could also try to exploit RSCE and back gate biasing to lower threshold voltage. |
Title: Re: Design of Rail-Rail OTA in 45nm Process Post by neoflash on Apr 4th, 2008, 8:04pm ACWWong wrote on Apr 4th, 2008, 5:42am:
Hi, Wong: Thanks for the head up. I was always trying not use that technique because they look risky. Is this inevitable choice? |
Title: Re: Design of Rail-Rail OTA in 45nm Process Post by loose-electron on Apr 10th, 2008, 1:44pm Typical threshold setting is 20% to 40% of the Vpower. Thats a "got to have" to get generic CMOS logic to plug and play. What you are stuck with is closer to 50% which makes life difficult at best. Can you request a secondary power supply at a higher voltage? (without violating Vgs restrictions?) Can you create your own power supply by charge pumping? There are ways of doing circuits with only three elements stacked power to rail, but things like cascodes and similar are not going to be in your tool bag. |
Title: Re: Design of Rail-Rail OTA in 45nm Process Post by ACWWong on Apr 12th, 2008, 1:58pm neoflash wrote on Apr 4th, 2008, 8:04pm:
I don't see it as risky, if the device models in your pdk are good. |
Title: Re: Design of Rail-Rail OTA in 45nm Process Post by kiran123 on Apr 14th, 2008, 10:02pm ACWWong wrote on Apr 12th, 2008, 1:58pm:
Hi Experts, Can anyone provide me Input Rail-to Rail opamap design steps for the figure attached herewith along with proper o/p summing ckt ( is from Ieee paper [i]"A Compact Power Efficient 3V CMOS Rail-to- Rail Input/Output Operational Amplifiers for VLSI Cell Libraries" by Ron Hogervorst , J.P.Tero, J.H.Hijsing [/i] ) or any suggested papers or documents to help me in this regard for designing steps even i referred books written by authors (opamp theory and design, low Voltage analog desin considerations ...etc) i have request to work on 0.18u technology Regards Kiran |
Title: Re: Design of Rail-Rail OTA in 45nm Process Post by neoflash on Apr 15th, 2008, 6:14am kiran123 wrote on Apr 14th, 2008, 10:02pm:
This is not rail-rail since output requires 2xVdsat to keep gain. |
Title: Re: Design of Rail-Rail OTA in 45nm Process Post by Berti on Apr 15th, 2008, 7:36am Neoflash is right: Kiran, The figure you attached doesn't show the rail-to-rail output stage, but only the first stage of the amplifier. For design steps: I think the amplifier is basically a two-stage amplifier with a folded-cascode first stage (with PMOS and NMOS diff. pair in parallel) and a class A push-pull second-stage. All those techniques are well covered by text books (e.g. P. Allen, CMOS Analog Circuit Design). Cheers |
Title: Re: Design of Rail-Rail OTA in 45nm Process Post by kiran123 on Apr 16th, 2008, 11:37pm Hi thanks Berti, I agree with you that input stage is one of the many techniques of rail to rail constant gm stage and whereas o/p is not o/p rail to rail one , at present i am looking the design steps of this input rail to rail constant gm stage + suitable and simple o/p stage as adder in this regard i don't think book allen is explained about ( input rail to rail constant gm techniques) if so do tell me chapter no( chapter 6 discusses with Class A and Class AB kind of opamap o/p stages not rail to rail input or o/p stage design rite?) if you can forward any good documents or referencess exactly to aid this design will be really helpful thanks Kiran |
Title: Re: Design of Rail-Rail OTA in 45nm Process Post by loose-electron on Apr 17th, 2008, 3:16pm Input rail to rail design is typically down with a PMOS differential pair and an NMOS differential pair structure - Each has its own current source, and each has its own "current mirror diode" active load. The second gain stage of each device mirrors out as a current, and then the signals from the two structures are summed together, and used to drive the output driver. The concept is roughly illustrated in the attached picture. Although this implementation uses diode connected loads, but the general idea is shown. |
Title: Re: Design of Rail-Rail OTA in 45nm Process Post by kiran123 on Apr 17th, 2008, 9:12pm loose-electron wrote on Apr 17th, 2008, 3:16pm:
Hi loose-electron, thanks for your post , this looks very different i have not seen this structure anywhere in the textbooks, so no idea on how to design to get constant gm over entire input common-mode range i have doubt regarding this can you explain the need of feeding the o/p (n1,n2) o/p of PMOS stage to NMOS stage loads @ p3,n4 through transistors P8 and n4 ? do let me know regarding this rail-rail design which is the best book? (i have refered many of them listed in above) but none of them gives design strategy as the one Allen holberg gives thanks kiran |
Title: Re: Design of Rail-Rail OTA in 45nm Process Post by neoflash on Apr 18th, 2008, 6:54am loose-electron wrote on Apr 17th, 2008, 3:16pm:
Doing this design in 45nm becomes extremely difficult... |
Title: Re: Design of Rail-Rail OTA in 45nm Process Post by Berti on Apr 20th, 2008, 10:18am Hi Neoflash, Would you please comment why you think that this structure might be difficult to realize in 45nm. Regards |
Title: Re: Design of Rail-Rail OTA in 45nm Process Post by kiran123 on Apr 20th, 2008, 9:47pm neoflash wrote on Apr 18th, 2008, 6:54am:
Hi Neoflash, i am not going to do it in 45 nm , what i want from you guys is exact schematic architecture & its design techiniques ( if you have any docs) used to create Input Rail to Rail ampamp that's it Regards Kiran |
Title: Re: Design of Rail-Rail OTA in 45nm Process Post by Berti on Apr 21st, 2008, 12:07am Hi Kiran, I think people got that. But this discussion initially started with OTA design in 45nm and I think we should come back to that (very interesting) topic since it will affect most of us analog designers (sooner or later). Your question on the other hand is very specific ... and unfortunately I have never designed a rail-to-rail input stage. Regards |
Title: Re: Design of Rail-Rail OTA in 45nm Process Post by RobG on Apr 21st, 2008, 1:36am neoflash wrote on Apr 2nd, 2008, 7:39am:
sounds like fun... I can't remember all of the dates/authors, but... back gate input (see Kinget's work) floating gate in series with input pair (Hassler/Georgi Tech may be a good start) charge pump up the source/gate of tail current source (JSSC article) "natural/native" NMOS (0 Vt)... ISSCC Cap level shifting (Gieger's CICC stuff ~2003) Use inverting configurations so the input common mode is constant. This is the best performing config. long time ago I did a SC circuit that sampled the Vgs of the input pair devices during the first phase (just switch both caps to the tail current source, while having the other ends connected to the input gates), and then put them in series with the gate during the second phase. This made the opamp rail/rail with canceled offset. |
Title: Re: Design of Rail-Rail OTA in 45nm Process Post by neoflash on Apr 21st, 2008, 6:02am Berti wrote on Apr 20th, 2008, 10:18am:
diode connected load device will consume too much voltage head room, thus input transistor pair easily enter triode region. |
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