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Modeling >> Semiconductor Devices >> The NPN Tr in 0.5um CMOS process
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Message started by dandelion on Apr 7^th, 2008, 8:23pm

Title: The NPN Tr in 0.5um CMOS process
Post by dandelion on Apr 7^th, 2008, 8:23pm

Hi,
I am deisgning an block which is PECl output. I found my process provide an NPN Tr and so I intend to use it to implement the PECL level. The NPN Tr is N+/P/NWELL topology. The base is located in the NWELL.

I communicated with the foundr, they said although this device is availble, it is not tested ever, so they can not guarantee if it have any risks. They said the beta of this device is 20 or so.

Would you pls. give any advice in using this device? Any risks ? What about its permance in mass production?

Thanks

Title: Re: The NPN Tr in 0.5um CMOS process
Post by loose-electron on May 15^th, 2008, 12:16pm

A little confusion on what you have there, but as a general rule, if you can avoid using unsupported and untested devices in a process, thats a very good thing.

The bipolar structures in CMOS are often used for designing bandgaps but thtere the frequency response and beta of the device are not critical.

- Jerry

Title: Re: The NPN Tr in 0.5um CMOS process
Post by Geoffrey_Coram on May 16^th, 2008, 6:37am

Risks would be: if the device completely fails to act as a transistor, the foundry will still make you pay for the wafers because it's not a supported device.

You might want to have a look at the masks that make it up and how they might go bad. Eg, what happens if the N+ implant goes too deep and shorts out the NPN: will this also cause a supported device to fail? In this case, I think you wouldn't have to pay for the wafers.