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Design Languages >> Verilog-AMS >> Question about SH VerilogA model
https://designers-guide.org/forum/YaBB.pl?num=1207826894

Message started by bmwsky on Apr 10^th, 2008, 4:28am

Title: Question about SH VerilogA model
Post by bmwsky on Apr 10^th, 2008, 4:28am

Dear All
I've already read the "Simulating switch-capacitor filters with SpectreRF" written by Ken Kundert. And I found two questions that I can't settle.

1. In the guide, Ken give the SH VerilogA model below:
-------------------------------------------------------------
`include "discipline.h"
`include "constants.h"

module sh (Pout, Nout, Pin, Nin);

input Pin, Nin;
output Pout, Nout;
electrical Pin, Nin, Pout, Nout;
parameter real period=1 from (0:inf);
parameter real tdelay=0 from [0:inf);
parameter real aperture=period/100 from (0:period/2);
parameter real tc=aperture/10 from (0:aperture);

integer n;
real tstart, tstop;
electrical hold;

analog begin

// Determine the point where the aperture begins;
n = ($abstime - tdelay + aperture) / period + 0.5;
tstart = n*period + tdelay - aperture;
@(timer(tstart));

// Determine the time where the aperture ends;
n = ($abstime - tdelay) / period + 0.0;
tstop = n*period + tdelay;
@(timer(tstop));

// Implement switch with effective series resistence of 1 Ohm
if (($abstime > tstop - aperture) && ($abstime <= tstop))
I(hold) <+ V(hold) - V(Pin, Nin);
else
I(hold) <+ 1.0e-12 * V(hold);

// Implement capacitor with an effective capacitance of tc
I(hold) <+ tc * ddt(V(hold));

// Buffer output
V(Pout, Nout) <+ V(hold);

// Control time step tightly during aperture and loosely otherwise
if (($abstime >= tstop - aperture) && ($abstime < tstop)) begin
$bound_step(tc);
end else begin
$bound_step(period/5);
end

end
endmodule
---------------------------------------------
why he use the "tc=aperture/10 "to set the capacitor? why not use a fixed capacitor??

2. In the guide, he told that if you would like to check the discrete time Gain response of the SC circuit, you should add a sample and hold circuit as described above. However, due to the sinc function of the SH, the output of the continues gain checked by PAC will change, esspecially the NULL point of the sinc. So, my question is how to check the discrete response by SpectreRF without adding a SH circuit after the output??

Thank you!!!

BMWSKY

Title: Re: Question about SH VerilogA model
Post by Marq Kole on Apr 10^th, 2008, 8:08am

Hi,

Answer to 1: the capacitance is related to the aperture - when the aperture changes through the parameter setting the capacitance value has to change with it as this hold capacitor has to be charged within the aperture time. To small and it would discharge too fast outside the aperture time; too large and it wouldn't charge up to the required level.

You can see for yourself what a fixed capacitor would do by setting up a test bench for this circuit and vary the aperture parameter value while passing a fixed value for the tc parameter value.

Cheers,
Marq

Title: Re: Question about SH VerilogA model
Post by bmwsky on Apr 10^th, 2008, 10:20pm

Thank you Marq,

I'v already test the SH as you said, it works. However, I found that the DC gain of PAC simulation is several dB less than the trans simulation when using the frequency near dc to test. I'm wondering what's going on?

BMWSKY

Title: Re: Question about SH VerilogA model
Post by Ken Kundert on May 16^th, 2008, 12:16pm

PAC includes the effect of the duty cycle when computing DC gain, whereas people often ignore the fact that the signal is only present part of the time and just examine the peaks when computing the DC gain.

-Ken