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Design >> Analog Design >> Transistor reliability in VCOs
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Message started by doho on Apr 11^th, 2008, 7:19am

Title: Transistor reliability in VCOs
Post by doho on Apr 11^th, 2008, 7:19am

Suppose your design kit documentation says that a transistor is not allowed to see
any voltages above VDD between any two terminals (including the bulk) if the reliability
as stated in the documentation is guaranteed to be met.

Now consider the common VCO topology with the center tap of the inductor connected to VDD, the
switching NMOS transistors below the inductor and a tail current source. The (voltage at a specific
point in time ) between the drain and the bulk of the switching NMOS transistors for this VCO topology will be
more than VDD since the oscillation amplitude typically is in the order of a few hundred
millivolts

Is this not a problem when considering reliability since the drain-bulk voltage will be
higher than VDD?

Title: Re: Transistor reliability in VCOs
Post by imd1 on Apr 11^th, 2008, 9:01am

You are right. That is why this configuration can only be used if you use a lower voltage for Vdd.
Use PMOS and CMOS core, or feed NMOS from current source at the top.

Title: Re: Transistor reliability in VCOs
Post by loose-electron on Apr 17^th, 2008, 3:28pm

the question that you are asking is very unique to the particular foundry process that you are on

Do designers go outside the power and ground maximum limitations of a foundry process? Yes, all the time, but you need to understand the particular specifics of those limitations and what "designing outside the box" may cause.

Suggest that you define what you are doing and get it reviewed with your expert on the foundry process and its restrictions.

Jerry

Title: Re: Transistor reliability in VCOs
Post by Geoffrey_Coram on Apr 22^nd, 2008, 12:54pm

doho wrote on Apr 11^th, 2008, 7:19am:

Is this not a problem when considering reliability since the drain-bulk voltage will be
higher than VDD?

Is the D-B junction a concern because of hot electrons that could end up trapped in the oxide interface?

Rather than oxide breakdown from a high VGS or VGB?

Title: Re: Transistor reliability in VCOs
Post by Hyvonen on May 17^th, 2008, 2:17am

Depending on the bias conditions and the oscillation amplitude of the VCO in question, drain-bulk voltage might not exceed VDD after all. Looking at the schematic, it seems that NMOS bulks are tied to their sources (triple-well process?), so bulk DC voltage is VDD-Vgs,nmos. If the oscillation amplitude is really high, gate-bulk/drain/source voltage may exceed breakdown limit, but otherwise this circuit might work fine.

Instead of looking at voltages as referenced to ground (or VSS/0V etc.), what really matters is what voltages (=potential differences) the transistor "sees." Look at the gate-drain, gate-bulk and gate-source voltages; if they are all below VDD, you're OK.

(Note that whenever one starts employing bulk bias tricks to extend operating voltage ranges, start-up should be planned in a way that the critical voltages are not exceeded at any point.)