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Design Languages >> Verilog-AMS >> Voltage Regulator
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Message started by Croaker on Apr 11^th, 2008, 2:36pm

Title: Voltage Regulator
Post by Croaker on Apr 11^th, 2008, 2:36pm

Does anyone know of a voltage regulator model? Currently I'm using a non-ideal op-amp wired up as a unity-gain amplifier. This actually works fine except that it takes around 1 us of sim time to reach steady state. Perhaps my real goal is to have a realistic model (you see dips when charge is pulled) that can settle quickly. I'm open to suggestions!

Thanks!

Title: Re: Voltage Regulator
Post by Stefan on Apr 12^th, 2008, 12:49am

That stronlgy depends on the schematic implementation you're trying to model.
If you're using a simple bucket converter, try to model it as such.
Your problem reaching steady state can be solved using initial statements ...

Title: Re: Voltage Regulator
Post by Croaker on Apr 12^th, 2008, 2:22pm

The schematic is an opamp driving a PMOS to source current through a two resistor string. One terminal of the opamp is a reference voltage and the other is tied between the two resistors. The regulator output is at the drain of the PMOS.

I'm not clear on how initialization statements could help. The regulator output is initially at the desired value. With a period switched-cap load, e.g. the regulator power an inverter switching high and low (charging and discharging a cap). As soon as the first switching event happens the output of the regulator drops but does not recover. Eventually the voltage does recover enough to reach a steady state with an average output voltage that is desired.