The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design >> Mixed-Signal Design >> Transient noise and the basic "sw-cap resistor"
https://designers-guide.org/forum/YaBB.pl?num=1208425773

Message started by DaffyDuck on Apr 17^th, 2008, 2:49am

Title: Transient noise and the basic "sw-cap resistor"
Post by DaffyDuck on Apr 17^th, 2008, 2:49am

Hi,

Simulation set-up: (A) gnd -- res -- sw ----- (B) gnd -- res -- sw -------- sw -- res -- gnd
(ck) | (ck) | (ckb)
cap cap
| |
gnd gnd
res = 500 Ohms (noise turned on)
sw = verilog-A model, noiseless
cap = 300f

For (A) and (B), I turned on the "trans noise" option in ADE and set noisefmax to 10G, and then ran a 10u transient sim. I then used the "rms" function in Calculator on the voltage across the cap.

For (A), the rms voltage is about 108uVrms, close to the theoretical value of 117uVrms ( sqrt(kT/C) of 1pF cap is 64uVrms ). For (B), I got the same number! I was expecting sqrt(2) * 117 uVrms, since there are 2 clock phases, 2 different resistors, and hence no correlation on the 2 noise generators from res.

Can I use the rms function this way to compute the sampled kT/C noise, or .... what's really the problem?

Daffy

Title: Re: Transient noise and the basic "sw-cap resistor
Post by DaffyDuck on Apr 18^th, 2008, 6:57am

It does not work as expected because the charge that is sampled in clock phase "clk" will be discharged in clock phase "clkb".... :-[