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https://designers-guide.org/forum/YaBB.pl Modeling >> Behavioral Models >> comparator modelling - error during simulation https://designers-guide.org/forum/YaBB.pl?num=1208865577 Message started by Pavel on Apr 22nd, 2008, 4:59am |
Title: comparator modelling - error during simulation Post by Pavel on Apr 22nd, 2008, 4:59am Hello, Here is AMS-model of comparator: Code:
At the picture below there are waveforms. Comparator output is connected to comp signal. INP is connected to envlp, INN - to dac_out. As you can see at the picture, after 2nd transition ('0'->'1'), output is frozen at '1'. How to avoid this problem. Thanks. Pavel. |
Title: Re: comparator modelling - error during simulation Post by Stefan on Apr 22nd, 2008, 6:42am Maybe this is a timing issue of the solver. Try to set max timestep or use an appropriate $bound_step in your model. |
Title: Re: comparator modelling - error during simulation Post by Pavel on Apr 22nd, 2008, 7:27am Thank you for response, Stefan I can't use $bound_step as I have no analog costruction in this configuration. Finally I resolved the problem. Here is code that works: Code:
Regards. Pavel. |
Title: Re: comparator modelling - error during simulation Post by Stefan on Apr 22nd, 2008, 7:37am Hi Pavel, your code generally does the same as the $bound_step function would do. It makes the analog solver produce an calculation closer to the crossing, so that it can be detected from the digital part. If you use wavescan to plot your first grafic you might see that there is no analog waveform crossing at the second falling edge. Can you confirm that ? There should be a better way to make a working code than your (well working, but pretty difficult to read) code. Regards, Stefan |
Title: Re: comparator modelling - error during simulation Post by Ken Kundert on Apr 22nd, 2008, 2:35pm Try tightening the tolerances on the cross functions. -Ken |
Title: Re: comparator modelling - error during simulation Post by jbdavid on Aug 27th, 2008, 1:10am or try writing it as a single cross statement with tolerances initial OUT = V(INP,INN) > 0; always @(cross(V(INP,INN),0,vtol,ttol)) OUT = V(INP,INN) > 0; But you do need a decent circuit feeding you INP and INN or you won't get enough timesteps on the analog side anyway.. above is an interesting function to look at too. |
Title: Re: comparator modelling - error during simulation Post by jbdavid on Aug 27th, 2008, 1:19am your working model is effectively initial OUT = V(INP,INN) >0; always @(cross(OUTa)) OUT = OUTa >0; analog OUTa <+ (V(INP,INN) >0)? 1:-1; endmodule so the cross statement in the analog block only forces a timestep at the crossing, but equation (not inside the cross) ALSO forces a timestep there because of its discontinuous nature (which is probably going to cause a problem in a larger simulation. ) |
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