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Design >> RF Design >> High Frequency Divider
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Message started by randyliu on Apr 23^rd, 2008, 10:46am

Title: High Frequency Divider
Post by randyliu on Apr 23^rd, 2008, 10:46am

Hi all:
Recently,I have to design a 4-divider based on D-flipflop(master-slave structure).The input frequency is above 5GHz.
Now I burn totally 13mA current to realise it.But I find if the load capacitor exceed 5 fF,it can not work correctly.
And another interesting thing is that even though the input clock is only 10mV,it also works,however the input signal is 200mV.
So what can I do to improve it?

Title: Re: High Frequency Divider
Post by didac on Apr 23^rd, 2008, 12:12pm

Hi,
A capacitance loading this kind of dividers could be a real problem, you must codesign a buffer to isolate the divider from the load(with a small transistor as the input of this buffer to avoid this loading). Also in the layout you must pay attention to the parasitics of the output lines(believe me I expended 4 hours optimizing the outputs of one of this dividers at layout level).
About that a tiny input makes the divider work it's not strange at all, I recommend that you do a 2-D parametric with the input signal(Vin and fin), if you plot like a contour with Matlab you will see the two operating regions(free running and locked divider) and you will also see how depending on the input frequency more or less input level is needed for the divider to work(you can also see if your frequency it's too close to the limit where the divider will stop working).
Hope it helps,
PS:it's compulsory the use of a master-slave divider?,maybe it's worth the effort to see at an Injection Locking frequency divider(the problem it's the area overhead...)

Title: Re: High Frequency Divider
Post by randyliu on Apr 23^rd, 2008, 2:27pm

Greatly thanks to didac.
Injection locked divider indeed is a LC-oscillator.Because I need a pair of quadrature output signal,and also the relatively large area for inductor,I choose the D-flipflop based divider,although it consume more power.

Title: Re: High Frequency Divider
Post by chase.ng on May 10^th, 2008, 8:48pm

Hi,

Is your dividers CMOS divider or SCL/ECL dividers? Do you mean you are designing a divide-by-4 divider?

Hm... I found that it is more tedious to design dividers without static timing analysis especially in large synchronous divider that has many functional options at high frequency. I have to manually look for the timing margin from simulation result for all the flops in the circuits.

You mentioned that your circuit will not work when you attached a 5fF capacitors as your load so it seems to me you have a synchronous design. If timing, noise and power is not an issue, I would suggest simpler design that is asynchronous i.e. cascade 2 simple and identical divide-by-2 together so that optimization and functional check is main on the first critical divider. The 2nd divider will most likely to work at lower frequency and it also serve as a buffer that decouple your critical first divider from your load. That will certainly reduce your risk and shorten the design time.

We have a large synchronous design before and we really have a tough time to ensure it is fully-functional. As mentioned by didac, layout optimization is really crucial.

Hope that helps.

Regards,
Chase

Title: Re: High Frequency Divider
Post by randyliu on May 12^th, 2008, 5:15am

I have solved problems now.
By using a ring osc based injection locked divider,it is easy to implement a divided by 4 frequency divider.I firstly design a ring oscillator works at 1.9GHz,then inject the 7.2GHz signal to the ring osc.By injection locking,the oscillator switch to work at 1.8GHz.With 4 stage structure,I got a pair fo almost quadrature output I/Q signal.

Thanks to all!