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Design Languages >> Verilog-AMS >> Macros inside Macros in Verilog-A for Cadence
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Message started by designerjoe on Apr 25^th, 2008, 9:12am

Title: Macros inside Macros in Verilog-A for Cadence
Post by designerjoe on Apr 25^th, 2008, 9:12am

I am creating Verilog-A models for simulation in Cadence and Spectre and would like to create macros that incorporate other macros and/or contants.

It should be possible to define one macro as result of another one and one or several operations such as:

`define WORD 2
`define LONGWORD (4*WORD)

This seems all well and good until one actually tries to use the macro `LONGWORD in the code.
The parser then gives an error message suggesting that LONGWORD uses an undeclared identifier: WORD.

The end of the error message reads like this:
Encountered undeclared identifier: WORD. Declare the
identifier before using it.

This isn't actually the macro I am going for but unless I can get something as simple as the example above working there is no chance to get anything really productive in place.

Could someone please tell me if this is an intended limitation of the compiler directives for Cadence or if I'm missing a vital point in the syntax rules?

Title: Re: Macros inside Macros in Verilog-A for Cadence
Post by patrick on Apr 25^th, 2008, 9:21am

You need:

`define WORD 2
`define LONGWORD (4*`WORD)

Patrick

Title: Re: Macros inside Macros in Verilog-A for Cadence
Post by designerjoe on Apr 25^th, 2008, 9:48am

Cheers Patrick!

That works.
I was mislead by the section "`if `MACRO is Not Allowed" in the Cadence Verilog-AMS Language Reference.

Best regards
Joe