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Design >> Mixed-Signal Design >> divide-by-2 circuit or duty cycle corrector?
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Message started by Monkeybad on May 6^th, 2008, 1:03am

Title: divide-by-2 circuit or duty cycle corrector?
Post by Monkeybad on May 6^th, 2008, 1:03am

Hello, everyone!
In order to generate a 50% duty cycle clock, there is a divide-by-2 circuit in PLL.
Sometimes it is called "TFF". But the VCO need to oscillate at twice as high as the desired clock.
This method is simple but waste power and makes VCO hard to design especially for very high clock frequency.
Another circuit called DCC (Duty Cycle Corrector) can be used to achieve 50% duty cycle clock.
It saves more power but maybe introduces jitters in the output clock.
Which method is more often used in a PLL? :-/
Thanks!

Title: Re: divide-by-2 circuit or duty cycle corrector?
Post by ywguo on May 8^th, 2008, 4:46am

Hi Monkeybad,

First, I don't think a duty cycle corrector must increase jitter significantly. At least the additional jitter is not larger than a divide-by-2.
Second, a 2X frequency VCO + divide-by-2 doesn't mean 2X times power logically. For eg. a VCO make of N CMOS inverter, say INVX1, runs at 1X frequency while a VCO made of 2N CMOS inverters (INVX1) runs at 2X freuquency. They consume the same power because the inverters toggle 2N times in the period 1/(2X frequency). Intuitively, that is due to the inverter does not consume static power. If a VCO is made of the delay cell with static current, say a differential buffer. Assume all the differential buffers are of the save size and the same delay time, a 2X frequency VCO made of the differential buffers consume half the power of 1X frequency VCO because a 2X frequency VCO has half quantity of the 1X frequency VCO.
Third, it is complicated to choose between 2X VCO and 1X VCO. The decision depends on the jitter requirement and other specific design requirement.

Best regards,
Yawei

Title: Re: divide-by-2 circuit or duty cycle corrector?
Post by Monkeybad on May 9^th, 2008, 1:37am

Hi, ywguo!
First, as I know, the jitter usually increases when the circuit is much complicated, but not always be true. In this point of view, some duty cycle correctors using feedback control are much complicated than the divide-by-2 circuit, so I think it maybe increase the jitter. Well, if it is not, the things become much better, right?
Second, I don't understand why you say 1X and 2X frequency VCO consumes the same power.
If you want to change the oscillating frequency of a VCO, you turn down or up the current of the delay cell rather than change the stage of the delay cell, isn't it?
Could you explain it in more detailed?

Title: Re: divide-by-2 circuit or duty cycle corrector?
Post by chase.ng on May 10^th, 2008, 9:11pm

Hi,

I agree with Yawei that it is very complicated to choose between 2X VCO and 1X VCO. In RF application, the VCO frequency is carefully planned to mitigate spurs and inteference. The requirement of having a DCC or divider often comes as the result of the frequency planning and the jitter performance of the VCO at the frequency of interest.

Some DCC are considerably low noise, i.e. they introduce noise that is not much more than a simple buffer depends on the overall design of the PLL and DCC. However, a divide-by-2 normally gives better 50% duty cycle than DCC as far as i know.

Regards,
Chase

Title: Re: divide-by-2 circuit or duty cycle corrector?
Post by keikei on May 13^th, 2008, 8:55am

For 2X VCO, even if the power consumption is not increased, usually its VCO gain will double, which I think is not preferable.

Title: Re: divide-by-2 circuit or duty cycle corrector?
Post by loose-electron on May 19^th, 2008, 2:26pm

both methods work.
DCC tends to be used more when power consumption is the most important
div-2 tends to be used more in RF design where duty cycle in a mixer is critical.