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Design Languages >> Verilog-AMS >> model of counter (Verilog-A)
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Message started by mus on May 7^th, 2008, 9:52am

Title: model of counter (Verilog-A)
Post by mus on May 7^th, 2008, 9:52am

Hello everybody,
Thank you in advance at which can help me to model in Verilog-A a counter.
In fact I need a binary-coded Verilog-A just for a test bench of my circuit. The specifications which meet this binary are:
1. A single input for counting the pulses
2. Multichannel 8-bit (ouput 8-bits)
3. With a reset active on the low level.
4. After its maximum value (255) it takes the value 0 (ie modulo 256)
Just for your information I have modelled the counter before relying on scales the flip flop D, JK, T modelled on Verilog-A. The counter modeled in this way works well, but I wonder is there a simpler way for to model it, as in the case of VHDL and Verilog.

Thank you very much,
best regards

Title: Re: model of counter (Verilog-A)
Post by jbdavid on Jun 19^th, 2008, 9:45am

yes there are simpler ways to do behavioral modules..

ie in VERILOG you'd do

module counter8(
input clk, rst_b,
output [7:0] count);
integer i_count = 0;
always @(posedge clk) i_count = (i_count+1)%1<<8;
assign count = i_count && !rst_b;
end module;

you can get quite close to this behavior in Verilog-A
-- the result is left as an exercise for the student!
* ---