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https://designers-guide.org/forum/YaBB.pl Design >> Mixed-Signal Design >> why use two switchs in the sampling period? https://designers-guide.org/forum/YaBB.pl?num=1210257840 Message started by lxw1983 on May 8th, 2008, 7:43am |
Title: why use two switchs in the sampling period? Post by lxw1983 on May 8th, 2008, 7:43am this is a sigma-delta ADC,why use two swichs (/S1,/S1D)in sampling period? |
Title: Re: why use two switchs in the sampling period? Post by Stefan on May 8th, 2008, 7:52am strongly looks like DC offset cancellation ... |
Title: Re: why use two switchs in the sampling period? Post by lxw1983 on May 8th, 2008, 7:52am Hope someone can help me ,thanks ! |
Title: Re: why use two switchs in the sampling period? Post by lxw1983 on May 8th, 2008, 7:58am DC offset cancellation?what mean ?I'm sorry I can't understand. |
Title: Re: why use two switchs in the sampling period? Post by ywguo on May 21st, 2008, 12:12am Hi lxw1983, Would you please post a timing diagram of those switches? Yawei |
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