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Simulators >> Circuit Simulators >> DAC SFDR measurement in Tanner
https://designers-guide.org/forum/YaBB.pl?num=1210293984

Message started by arjunpcet on May 8^th, 2008, 5:46pm

Title: DAC SFDR measurement in Tanner
Post by arjunpcet on May 8^th, 2008, 5:46pm

hi all....I have designed a 10 bit 100 MHz current steering DAC in Tanner EDA.... To measure SFDR i need to use an ideal ADC at the dac input.....But the problem is that Tanner doesnt support verilog A models for ideal ADC...and i cant find a spice netlist for an ideal 10 bit ADC....so plz do help me....
thanks in advance

Title: Re: DAC SFDR measurement in Tanner
Post by patrick on May 8^th, 2008, 10:10pm

Version 13.0 supports Verilog-A (LRM 2.2).

Patrick