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Design Languages >> Verilog-AMS >> problem with transition filter in verilogA
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Message started by ssdfz on May 12^th, 2008, 10:55pm

Title: problem with transition filter in verilogA
Post by ssdfz on May 12^th, 2008, 10:55pm

Hello Everyone:

By browsing through this forum, I realize that there are many true expert of VerilogA. I was hesitant about posting my problem as I am afraid it would be too trivial for you. But this issue has been really bothering me for couple of days… I am trying to model the gate capacitance of a mosfet; assuming the Cg = Cgoff when Vgs < Vth and Cg = Cgsat when Vgs > Vth. Below is my code. It really just needs the first two inputs and the latter three are just for debugging. The code works okay until the line above the one with (***). Without a transition for q, it seems that the simulator will complain. I added the transition filter hoping to smooth the transition. However, it turns out that V(out) is just a flat line whereas V(qout) is switching. Could anyone give your valuable suggestion? To me it seems that the transition filter is just not working properly here.
Second question: the simulation I am using is hspice. When I switched to HSIM, it always complain with the syntax of @(above (v - vth) ). Anyone knows the reason?

`include "disciplines.vams"
module nmos_cap(p,n, cout, qout, out);

parameter real vth = 0.4 from (0:inf);
parameter real cgoff = 40f from (0:inf);
parameter real cgsat = 400f from (0:inf);
parameter real td = 0 from [0:inf);
parameter real tr = 100p from [0:inf);
parameter real tf = 100p from [0:inf);
inout p; electrical p;
inout n; electrical n;
output cout; electrical cout;
output qout; electrical qout;
output out; electrical out;
real c;
real q;
real v;
analog begin
v = V(p,n);
@(above (v - vth) ) //nmos is turing on in saturation region
c = cgsat;
@(above (vth - v) ) //nmos is off
c = cgoff;
q = c*v;
V(cout) <+ c;
V(qout) <+ q;
V(out) <+ transition(q, td, tr, tf); //(***)
I(p,n) <+ ddt(V(out));
end
endmodule

Erik

Title: Re: problem with transition filter in verilogA
Post by Geoffrey_Coram on May 13^th, 2008, 6:58am

ssdfz wrote on May 12^th, 2008, 10:55pm:

2nd first: "above" is a relatively new addition to the language, from LRM 2.2.

Back to your main question: I surely would expect a simulator to complain if the charge is discontinuous as a function of voltage. You should try to write some equation for "q" (not c! -- though you've got a linear cap, so that's not the issue here) that is continuous in voltage, and one that doesn't use events but is valid for all v.

In your current system, for v==vth - epsilon, you have q = cgoff * vth; for v==vth+epsilon, you have q = cgsat * vth. So, even for a very slow ramp of "v" across vth, you have a delta-q (I = dq/dt) of (cgsat - cgoff) * vth, which makes for a huge spike in current.

Title: Re: problem with transition filter in verilogA
Post by Ken Kundert on May 13^th, 2008, 7:00pm

First, you should never pass values that change continuously through a transition function. You should be passing c through the transition function, not q.
Second, you have created a time varying capacitor, so you should account for the charge that flows as a result of the time varying capacitance.

None of this explains why the simulator complained. Perhaps you can tell us what the complaint was?

-Ken

Title: Re: problem with transition filter in verilogA
Post by ssdfz on May 13^th, 2008, 11:32pm

Many thanks to Geoffrey and Ken for your insightful replies.
Geoffrey: I have got a reply from Synopsys AE which says the same thing as you pointed out: "above" is not supported by HSIM yet; "cross" is a workaround. I agree that a continuous equation describing Cg vs. Vgs will be better; two reasons I wanted to do piecewise linear model: 1.simple ( i dont know a particular equation on that except for curve fitting) 2. I thought the transition filter will sort of "soft" connect the curves around vth.
Ken: Thanks for pointing out my invalid usage of transition filter. I modified my code as shown below. I am not sure if i get your second point. Simulation shows that it fulfills my need, but I dont know if there are any hidden issues that I dont see since I am still learing VerilogA.

One thing I notice is that ceff will not be changing at all for cgoff = 40f and cgsat = 400f; my intuition is that the value is too small for transition filter to pick up; so I worked around by first multiplying 1e12 and then devide. Any scientific explanation/solution on that issue?

`include "disciplines.vams"
module nmos_cap_vams(p,n);
parameter real vth = 0.4 from (0:inf);
parameter real cgoff = 40f from (0:inf);
parameter real cgsat = 400f from (0:inf);
parameter real td = 0 from [0:inf);
parameter real tr = 100p from [0:inf);
parameter real tf = 100p from [0:inf);
inout p; electrical p;
inout n; electrical n;
real c;
real ceff;
analog begin
@(above (V(p,n) - vth)) //nmos is turing on in saturation region
c = cgsat*1e12;
@(above (vth - V(p,n))) //nmos is off
c = cgoff*1e12;
ceff = transition(c, td, tr, tf)*1e-12;
I(p,n) <+ ceff*ddt(V(p,n));
end
endmodule

Thanks

Title: Re: problem with transition filter in verilogA
Post by Geoffrey_Coram on May 14^th, 2008, 9:42am

Ken's second point was that you should have I = ddt(Q) = ddt(ceff *V(p,n)) because the current is the change in charge; your equation doesn't capture d(ceff)/dt, which will cause current.

Title: Re: problem with transition filter in verilogA
Post by ssdfz on May 14^th, 2008, 11:25am

Understood. Thanks for your explanation.