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Design Languages >> Verilog-AMS >> VerilogA simulation time
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Message started by ssdfz on May 19^th, 2008, 9:50pm

Title: VerilogA simulation time
Post by ssdfz on May 19^th, 2008, 9:50pm

Hi All:

When I run transient simulation for each individual verilogA block, the simulation time is pretty short (say around 0.01sec ~ 0.1sec for 3us transient). however, when I connect about 30 blocks together (most of them are verilogA model of digital gates, together with other models such as res, cap, comparator, switch), the total simulation time is about 40 sec for 3us transient. however, the full spice model will conclude within 10 sec. By looking at the output log file, it seems that verilogA model simulation takes much more iterations. I feel something wrong among the interface of blocks, but dont have much clue on what direction I need to debug. I tried to take care of discontinuity issue by feeding piece-linear output with transition filter, so the output didnt complain/warn about that.
As writing this post, I just have two ideas: 1. add large parallel resistance with capacitor, so that the node connecting the cap has DC ground; 2. change the discipline from electrical to voltage. But honestly I don't understand what's going wrong.

Could you please give some suggestions? I know it would be hard without seeing the code...

Thank you in advance
Erik

Title: Re: VerilogA simulation time
Post by Stefan on May 19^th, 2008, 11:24pm

There is a difference between time steps and iterations. I think it's possible that your transient statements produce more than necessary timesteps for the whole simulation time (depends on their accuracy settings).
You should provide a bit more information, like the two output logs and netlists.

Title: Re: VerilogA simulation time
Post by sheldon on May 20^th, 2008, 5:55am

Erik,

You don't really mention why are trying model a circuit that simulates in
only 10s. It does not seem like behavioral modeling is required to verify
the connectivity/functionality of the circuit. So the assumption is that you
are using the model to simulate a large more complex circuit. In that case,
you might want to consider the following. In general when using Verilog-A
for functional verification, it is useful to raise level of abstraction as you try
to model more complex functionality. For example, instead of modeling a
non-overlapping clock generator at the gate level, model it as a non-
overlapping clock generator, that is, simulate it as a block box.

If you can't post the code, can you post a schematic. It would be useful
for understanding whether re-partitioning is an option.

Best Regards,

Sheldon

Title: Re: VerilogA simulation time
Post by Geoffrey_Coram on May 20^th, 2008, 6:02am

I'd try to replace those transition() filters with smooth functions. Can you replace some of the V-A blocks with transistor-level and see if you can narrow down which of the V-A blocks is causing the most trouble? Or insert one V-A module at a time in the transistor level sim and see which one slows it down the most.

Title: Re: VerilogA simulation time
Post by ssdfz on May 20^th, 2008, 11:04am

Thanks all for the prompt response!

Stefan: the transient step I set for both spice and verilogA simulation is the same: .tran 0.1n 3.2u

Sheldon: I agree with you that the current ckt is not slow for spice simulation. I am currently just trying to mimic the behavior of the circuit (functionality and timing) so that the verilog-A block can be embedded in a larger model later. The thing I don't really understand is that I thought an accurate/more structural model will take longer time to simulation than a high level model, but it should still be faster than a pure spice netlist.. The main block that I am modeling is a comparator, two input sources are filtered with 1st RC filters before connecting to the input ports or the comparator. for one input source, it is selecting between two constant values through switches, whose control signal is the output of the comparator through some logic gates (so there are some feedbacks).

Geoffrey:
Could you be more specific on what you mean by smooth functions? I didn't deal with them before. I think what I am going to do now is to go back to the transistor ckts and replace blocks one by one as you suggested.

Thanks!
Erik

Title: Re: VerilogA simulation time
Post by byang on May 20^th, 2008, 2:18pm

Erik,

Our simulator, Gsim, has a debug option that can tell why and where a simulation takes many iterations. Usually that kind of option is for simulation R&D. If the simulator you are using has such kind of option, then you can use that to find out the problem.

Regards,

byang
http://www.gemini-da.com

Title: Re: VerilogA simulation time
Post by Geoffrey_Coram on May 21^st, 2008, 11:43am

You wrote something about smoothing the piecewise linear outputs with the transition filter. I'm imagining something like

if (x > 1)
iout = 1u;
else if (x > 0)
iout = 2u;
else
iout = 5u;

I(out) <+ transition(iout, 1n, 1n);

So, right at x==1 and x==0, there are discontinuities in the current. It would be better if you could write a function iout(x) that is continuous in x, and best if that function also had a continuous first derivative.

Title: Re: VerilogA simulation time
Post by ssdfz on May 21^st, 2008, 10:17pm

Thanks Byang, I will contact the vendor to see if hspice or hsim has the similiar debugging feature as you mentioned.

Hi Geoffrey:

Thanks for your explanation.
Are you suggesting to use functions such as tanh to achieve the waveform instead of piecewise linear transition filter? For example, will a continuous comparator such as http://www.eda.org/verilog-ams/models/continous_comparator.va be better/easier than a pwl comparator such as http://www.eda.org/verilog-ams/models/pwl_comparator.va for hspice to conclude the simulation when it is interconnected with other blocks?

Again, thank you for your time and opinion!
Erik

Title: Re: VerilogA simulation time
Post by Geoffrey_Coram on May 22^nd, 2008, 6:53am

Erik -
Since you reported an increase in iteration counts, yes, I think the continuous one would be better; with the pwl, the simulator could be bouncing back and forth between two linear regions, neither one of which gives the correct derivative information for converging with Newton-Raphson iteration.

Of course, if the block-by-block replacement points to a different module, you may want to look at how smooth that block is.

Title: Re: VerilogA simulation time
Post by ssdfz on May 22^nd, 2008, 9:53am

Understood, Geoffrey.

Just curious, for the example you mentioned, would it be helpful for simulator to converge if I add discontinuity at the switching point?
-->Code before:
if (x > 1)
iout = 1u;
else if (x > 0)
iout = 2u;
else
iout = 5u;

I(out) <+ transition(iout, 1n, 1n);

--> Code modified
iout = 5u;
@cross(x - 1, 1)) begin
iout = 1u;
$discontinuity(0);
end
@cross(x - 1, -1)) begin
iout = 2u;
$discontinuity(0);
@cross(x - 0, 1)) begin
iout = 2u;
$discontinuity(0);
end
@cross(x - 0, -1)) begin
iout = 5u;
$discontinuity(0);

I(out) <+ transition(iout, 1n, 1n);

I am asking this because for the multiple level pwl waveform, I guess it would be difficult to find a smooth function to represent it. (one way I can do is to use matlab to curve fit it) .

Thanks,
Erik

Title: Re: VerilogA simulation time
Post by Geoffrey_Coram on May 23^rd, 2008, 4:58am

I don't have any experience with $discontinuity; I don't know how (if?) simulator vendors have implemented it. (Most of my experience is with "compact models," which are supposed to be at least C³, if not C^∞.)