The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design >> Analog Design >> Offset compensation
https://designers-guide.org/forum/YaBB.pl?num=1211283253

Message started by manodipan on May 20th, 2008, 4:34am

Title: Offset compensation
Post by manodipan on May 20th, 2008, 4:34am

Hi Guys,
I am facing some problem for offset compensation in my circuit.The circuit is explained below:
It is a switched capacitor circuit where the charge transfer is done by a comparator and current source.The sampling phase is same like conventional opamp based case,but in transfer phase the comparator decides when to start and stop the transfer.There are two phses of transfer namely coarse and fine phase.Now all the components are modelled in VerilogA.Now due to the finite delay of the comparator there is some offset at output because of finite time when comparator detects and some action is taken.Now if input is some pulse,for some current source setting(fixed) offset is same and can becompensated by properly adjusting the period of fine transfer.but when input is a sinusoid,offset changes along with signal and the system is to be compensated for this varying offset.The circuit is single ended and the compensation should preferably done by the same comparator.

Now we can't use output or input offset storage technique,because it requires an opamp...so i am puzzled about what to do????can u guys giv e me some idea to compensate for this circuit??Thanks in advance.

Title: Re: Offset compensation
Post by jiesteve on May 21st, 2008, 5:08pm

I'm having trouble picturing the circuit.  Perhaps you could post a conceptual schematic.

Title: Re: Offset compensation
Post by vivkr on May 21st, 2008, 11:14pm


manodipan wrote on May 20th, 2008, 4:34am:
Hi Guys,
I am facing some problem for offset compensation in my circuit.The circuit is explained below:
It is a switched capacitor circuit where the charge transfer is done by a comparator and current source.The sampling phase is same like conventional opamp based case,but in transfer phase the comparator decides when to start and stop the transfer.There are two phses of transfer namely coarse and fine phase.Now all the components are modelled in VerilogA.Now due to the finite delay of the comparator there is some offset at output because of finite time when comparator detects and some action is taken.Now if input is some pulse,for some current source setting(fixed) offset is same and can becompensated by properly adjusting the period of fine transfer.but when input is a sinusoid,offset changes along with signal and the system is to be compensated for this varying offset.The circuit is single ended and the compensation should preferably done by the same comparator.

Now we can't use output or input offset storage technique,because it requires an opamp...so i am puzzled about what to do????can u guys giv e me some idea to compensate for this circuit??Thanks in advance.


Looks to me like a basic problem when using this structure. I would try one of the two things:

1. Try to speed up the comparator. This runs into power and is also not easy since your scheme obviously depends on the comparator being able to realize a very large gain.

2. If possible, try to reduce the current of the current source. This is going to work when your input signal in moving relatively slowly, which it would seem is not the case since
you worry about the signal-dependent offset.

3. Alternatively, if the signal-dependent offset dominates over the fixed comparator offset, you can try to use a replica comparator which does the same thing as the main comparator and see
if you can devise some sort of cancellation scheme (I don't have the details in my mind but I imagine that it would be possible). The residual fixed offset and offset difference between the 2 comparators
should be harmless in comparison.

Hope this helps.

Regards
Vivek

Title: Re: Offset compensation
Post by manodipan on May 27th, 2008, 2:24am

Hi Vivek,
Thanks for your response,i don't get you ,it would be better if you send me some reference on cancellation technique using replica structure,what is the basic philosophy of that technique??

Title: Re: Offset compensation
Post by vivkr on May 27th, 2008, 6:45am

Hi,

I could not tell you offhand what sort of replica structure to use for cancelling yout signal-dependent offset but let me think about it. The basic idea
of replica-based cancellation is to have a second copy of the main circuit whose errors you are trying to correct and allow the input signal to operate
on it. This copy might possibly be scaled down in size/current in most cases. If well designed, the replica should see the same systematic error as the
main copy. If you can now extract the information of interest from this replica (in this case the signal-dependent offset) and use it cancel the error in the
main circuit, then your job is done. The important part of course is to be able to do these 2 things.

In principle, the main circuit could act as its own replica in the extreme case by switching between normal operation mode and error measurement mode.
There are plenty of similar circuits which rely on such or similar methods. I will see if I can send you a link to some such design. Standard examples
would be time-shifted-CDS (correlated double sampling), normal CDS (same circuit reconfigured to perform both functions) or the famous case of
the negative feedback amplifier of course, which suppresses its own distortion by feeding back information about the output to the input, realizing accurate
closed-loop gain.

Regards
vivek

The Designer's Guide Community Forum » Powered by YaBB 2.2.2!
YaBB © 2000-2008. All Rights Reserved.