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Measurements >> Phase Noise and Jitter Measurements >> Jitter simulation for limiting amplifier
https://designers-guide.org/forum/YaBB.pl?num=1211489344

Message started by hpham100 on May 22^nd, 2008, 1:49pm

Title: Jitter simulation for limiting amplifier
Post by hpham100 on May 22^nd, 2008, 1:49pm

Hi,
I am designing a limiting amplifier, and tried to simulate jitter using pnoise analysis. My set up is like this:
--beat frequency : 4G
--output amplitude 400mVp-p (differential)
--input amplitude : from 2mV-400mVp-p (differential) (ideal sine wave from psin)
--pnoise setting : sweeptype = absolute, noisetype=jitter,threshold value=0, crossing direction=all, sweep from 1G->10G
Jitter(Jcc) results : 1) vin=2mV --> Jcc[Second][k=1]@(3G,5G)Hz:rms = 18p
2) vin=4mV --> 9.05p
3) vin=200mV --> 0.263p
4) vin=400mV --> 0.191p
So, jitter results seems to be strongly dependent on input amplitude ?? Is it right ??
I also run transient analysis with different input amplitude(from 2mV-->400mV), and check phase variation of output voltage(zero crossing)
-- on rising edge : delta ~ 2.75ps
-- on falling edge : delta ~ 0.91ps (Input Freq is 4GHz)
I am not sure about the relationship between jitter number using pnoise analysis and AM->PM number using transient analysis as above?
Could someone help me to clarify this.
Thanks alot.
ha
P.S: when running pnoise analysis from 1G to 10GHz, in the output log window I saw pnoise sweeping from 1G --> 10G TWICE !! Why is that??

Title: Re: Jitter simulation for limiting amplifier
Post by Stefan on May 22^nd, 2008, 1:52pm

Yes , the jitter depends on the input peak to peak amplitude.
That results from the fact that a higher amplitude leads to steeper slopes for the crossing, which makes them less sensitive to amplitude variations.
The difference between rising and falling edge may result from your circuit design and transistor specifications.

Regards,

Stefan

Title: Re: Jitter simulation for limiting amplifier
Post by hpham100 on May 23^rd, 2008, 11:34am

Dear Stefan,
I'm still confused. So, pnoise(jitter) does not take into account the effect of changing input level by itself, unless you change it and simulate again??
When varying input from 2mV to 400mV, in transient analysis, phase error is about 2.75ps while pnoise(jitter) difference is 18ps-0.191ps ~ 18ps
Is there any relationship between those numbers ??
thanks a lot,
ha