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https://designers-guide.org/forum/YaBB.pl Simulators >> AMS Simulators >> veriloga and symbol do not match properly https://designers-guide.org/forum/YaBB.pl?num=1211549097 Message started by horizon on May 23rd, 2008, 6:24am |
Title: veriloga and symbol do not match properly Post by horizon on May 23rd, 2008, 6:24am Hello the designer community, I am working with cadence. I have a symbol using a bus bn<12:0>, when I create a veriloga view , a pop up with the veriloga text concerning the view is generated. the bus is written as [12:0] bn. When I compile the veriloga view, cadence complains. The simulations are working but in the ciw windows I get ERROR: Terminal "bn<12:0>" is defined in veriloga text but not in symbol view. The terminal in symbol view is either missing or ignored. ERROR: Terminal bn<0:12> in symbol cell view is not defined in veriloga text. The terminal in symbol view is either missing or ignored. I don't understand, I tried generating the veriloga view from the symbol view, I tried to generate the symbol view from the veriloga view... same problem. The cdf definition seems ok ... If I change the order on the veriloga view [0:12] bn the compilation is clear but the simulation is crashing. "Netlister: Cannot find terminal 'bn<0:12>' on instance 'I4' in lib 'CDSPGA' cell 'testTOPVIEWPveri' view 'schematic'." Does somebody had such a problem ? have a nice day horizon |
Title: Re: veriloga and symbol do not match properly Post by jbdavid on Oct 9th, 2008, 6:27pm there are some default environment settings wrt bit orders.. this is something your cadence AE can help you with. |
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