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Modeling >> Semiconductor Devices >> problems for a mos transistor modeled in vhdl-ams
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Message started by alinalin19832007 on May 24^th, 2008, 2:48pm

Title: problems for a mos transistor modeled in vhdl-ams
Post by alinalin19832007 on May 24^th, 2008, 2:48pm

Im trying to simulate an transistor that is modeled in vhdl-ams in Cadence environment IUS 5.7. The problems is that this model works fine IUS5.5 but in IUS5.7 i have some oscilations in the moment I try to switch off.
Can explain anybody why is this thing ?
What are the difference between two IUS?

thank y very much
I hope u understand what i want to say? ;)

Title: Re: problems for a mos transistor modeled in vhdl-
Post by Geoffrey_Coram on May 27^th, 2008, 5:27am

Could be you're just getting lucky with one IUS. What does the capacitance model look like? Is it (correctly) formulated in terms of charge instead of capacitance * voltage? What happens to the channel charge when the device is suddenly turned off?

Title: Re: problems for a mos transistor modeled in vhdl-
Post by alinalin19832007 on May 29^th, 2008, 1:09pm

The model works fine vgs<vds+3V , i dont know why is that