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Design Languages >> Verilog-AMS >> current limiter in Verilog-A
https://designers-guide.org/forum/YaBB.pl?num=1211713371

Message started by icdes321 on May 25^th, 2008, 4:02am

Title: current limiter in Verilog-A
Post by icdes321 on May 25^th, 2008, 4:02am

I am writing a current limiter in Verilog-A. Should be simple but in simulation the results are not as expected. Any suggestions will be appreciated.

`include "discipline.h"
`include "constants.h"

module current_limiter(in,out);
inout in, out;
current in,out;
parameter imax = 100e-3;

analog
begin
@(initial_step) if (I(in,out) > imax) I(in,out) <+ imax;

end
endmodule

Thanks.

Title: Re: current limiter in Verilog-A
Post by Stefan on May 25^th, 2008, 5:08am

@(initial step) makes the simulator evaluate the next statement only once at the beginning of the simulation.
Your limiter simply does nothing for the rest of the simulation time.

Title: Re: current limiter in Verilog-A
Post by icdes321 on May 25^th, 2008, 6:18am

Stefan, Thank you. But adding "if (I(in,out) > imax) I(in,out) <+ imax; " does also not work.

module current_limiter(in,out);
inout in, out;
current in,out;
parameter imax = 100e-3;

analog
begin
@(initial_step) if (I(in,out) > imax) I(in,out) <+ imax;

if (I(in,out) > imax) I(in,out) <+ imax;

end
endmodule

Title: Re: current limiter in Verilog-A
Post by Geoffrey_Coram on May 27^th, 2008, 5:30am

Yikes! I don't think you've got the idea here at all. What about:

module current_limiter(in,out);
inout in, out;
current in,out;
parameter imax = 100e-3;
real iout;

analog
begin
iout = I(in);
if (iout > imax) iout = imax;
I(out) <+ iout;

end
endmodule

Title: Re: current limiter in Verilog-A
Post by Ken Kundert on May 27^th, 2008, 11:54am

The problem is more subtle than that. To build a reliable current limiter you cannot simply compare the output current against Imax, and then if above Imax, set the output current to Imax. Once you override the output current, it is no longer over Imax. This results in the state switching back and forth between limiting and not limiting on every iteration, which would cause convergence problems. A robust model can be found in the Verilog-AMS section of this site (www.verilog-ams.com). It is called "Current limited voltage regulator" and can be found in the functional Verilog-A models section.

-Ken