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Design >> Mixed-Signal Design >> Improving frequency resolution with Sigma-Delta
https://designers-guide.org/forum/YaBB.pl?num=1211996825

Message started by PKAT on May 28^th, 2008, 10:47am

Title: Improving frequency resolution with Sigma-Delta
Post by PKAT on May 28^th, 2008, 10:47am

Hello
My understanding of 1-bit Sigma Delta A-D converter is that the in-band quantization noise is suppressed due to high-pass filtering effect. This increases SNR, which may be interpretted as an increase in quantization bits. So in essence the information from analog domain has been converted to quantized domain, which is what A-D do.
This I believe I understand well.

In context of Digitally-controlled oscillators (DCOs), the digital sigma-delta modulator is used along the fractional bits. The Sigma-Delta modulator dithers the fractional control bits that go to the DCO. In one architecture each sigma-delta output goes directly to unique very small discrete capacitors of DCO. Inside the DCO the time-averaging takes place. As a result of dither/noise from Sigma-Delta modulator (often high-order), the outcome is increased frequency resolution. This increase in frequency resolution is what I do not understand. I can uderstand how sigma delta modulation noise (although low) will reduce the oscillation jitter due to slight scattering of instances when the capacitors are switched as the LC tank oscillates and therefore the noise is spread out. As a result there are no spurs corresponding to the reference frequency which implies improvement in Phase Noise in the vicinity of the oscillation frequency. But I fail to understand why the frequency resolution improves?

I would really appreciate an intuitive feedback.

Thank you very much

Title: Re: Improving frequency resolution with Sigma-Delt
Post by Stefan on May 29^th, 2008, 12:51am

You only mentioned one of the two aspects of sigma-delta AD converters.
The one you spoke about is noise shaping, but you shouldn't forget about oversampling, which leads to the higher resolution.
Since this is the same for the other question, you should make yourself familiar with it, maybe you'll then get the clue :)

Title: Re: Improving frequency resolution with Sigma-Delt
Post by Berti on May 29^th, 2008, 4:13am

Sigma-delta modulation high-pass filters the quantization noise. This noise has to be removed by
a low-pass filter somehow. This results in lower noise within the signal band.

Quote:

The Sigma-Delta modulator dithers the fractional control bits that go to the DCO.

Therefore, it is more than just dithering.

Title: Re: Improving frequency resolution with Sigma-Delt
Post by PKAT on May 29^th, 2008, 6:42am

Thanks for responding.
As I read and familiarize myself more with all these concepts, I believe I have made more progress in my understanding.
In ADC oversampling with 1-bit quantizer followed by low pass filtering leads to increased SNR and thus may be interepretted as higher resolution than 1-bit even though a 1-bit quantizer was used makes sense.

However Sigma-Delta in DCO where the modulator output goes to DCO's discrete capacitors seemed a little different and therefore I was confused.

Here is my evolved intuitive feel for sigma delta modulator in regard to the DCO.
Keeping in mind the fact that average o/p of the modulator is same as the average of it's input and that the averaging happens in the DCO itself at the capacitors.
Say the input of the modulator is N-bit and it's output of M bits => 2^N input levels are possible. That also implies that at the modulator o/p there will be as many corresponding average values that are attained with the help of M discrete capacitors. Hence the M capacitors are pulse width modulated to increase the effective number of capacitors. That is just like the Fractional-N PLL with sigma-delta modulator, where say N/N+1 divider is pulse width modulated to provide finer resolution.

So returning to DCO, it is now much more apparent to me how the resolution increased with Sigma-delta modulator while saving space (+advantages of dithering) by using M capacitors which is much smaller than having 2^N discrete capacitors. 2^N discrete capacitors may not be practical anyway.