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Simulators >> AMS Simulators >> Parameteric sweep of Verilog modules
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Message started by mattlohry on Jun 4^th, 2008, 3:07pm

Title: Parameteric sweep of Verilog modules
Post by mattlohry on Jun 4^th, 2008, 3:07pm

I was wondering if it is possible to sweep a parameter defined in a Verilog module via the parameteric sweep tool of ADE when using SpectreVerilog or UltraSimVerilog?

If not, is there any other way to get a similar result by a different approach?

Thanks for the assistance.

Title: Re: Parameteric sweep of Verilog modules
Post by jbdavid on Oct 9^th, 2008, 6:25pm

I'd use AMS if I were you..
if you set the instance parameter value to a DESIGN VAR (one of those ADE things) then you can sweep it..
as an example look at the bmslib busset8 verilogams model..
its designed exactly for this purpose..
(BTW bmslib is located in the same cadence install directory as ahdlLib)
--
jbd