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Design >> Analog Design >> Subthreshold related question
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Message started by solidrepellent on Jun 6^th, 2008, 2:09am

Title: Subthreshold related question
Post by solidrepellent on Jun 6^th, 2008, 2:09am

Hello all,

1) We know that the threshold voltages for NMOS (assume 130mV) and PMOS (assume 190mV) are different. When researchers say that a particular circuit (assuming a complementary CMOS circuit) operates at subthreshold level do they mean that it operates below the minimum of those two thresholds. In this case below NMOS threshold voltage level ?

2) When can we say that a sub-threshold circuit is working properly? Is it when the output swing is 10% to 90% of Vdd ? or is there any other criteria that needs to be looked at?

Assuming Vdd= 1.2V

Thanks in advance,
Naveen.

Title: Re: Subthreshold related question
Post by buddypoor on Jun 6^th, 2008, 5:42am

solidrepellent wrote on Jun 6^th, 2008, 2:09am:

For my opinion, if a circuitry is said to work at subtreshold level this belongs to both transistors. Do you think of circuits working in the log domain ? This is a typical subtreshold application.

Title: Re: Subthreshold related question
Post by solidrepellent on Jun 6^th, 2008, 6:06am

Well, as far as I know subthreshold regime is defined for a single transistor. If we are looking at a NMOS then it would be in subthreshold when Vgs<Vthn. Similarly for PMOS. But I have been reading some papers (http://mtlweb.mit.edu/researchgroups/icsystems/pubs/journals/2005_wang_jssc_jan.pdf) where they talk about threshold voltage of an FFT processor which can be scaled down. They run simulations by changing threshold voltage. I would like to know threshold voltage of what they are scaling down. Is it PMOS or NMOS or some kind of a nominal threshold voltage they found ?

Thank you all,
Naveen

Title: Re: Subthreshold related question
Post by thechopper on Jun 6^th, 2008, 8:27pm

Hello,

Typically when a circuit is said to work under sub-threshold both types of devices are under that condition: for instance a differential nmos pair biased with a tiny current will be under sub-threshold, and if a pmos acitve load is used then they most probably will be under sub-threshold. At Vdd=1.2v, in order not to have those pmos in subthreshold you would need a very small W/L ratio which might cause some headroom problems in this example.
Although such circuit can be considered to work under sub-threshold, that does not mean all its transistor are in such condition. Eventually you might have a combination of some of the working under subthershold and others that do not.

Hope this helps.
Tosei