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Design >> Analog Design >> Understanding ESD discharge
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Message started by Godfrey on Jun 6^th, 2008, 2:18pm

Title: Understanding ESD discharge
Post by Godfrey on Jun 6^th, 2008, 2:18pm

I have made a chip conform to ESD guidelines, but I am doing this blind since I dont understand why the rules are there. I have a digital Vcc and an analog Vcc, I also have VssD and VssA. I have power clamps from VccD to VssD and from VccA to VssA. On each input I also have two local clamps to its power rails..

So during ESD event when one IO is grounded (on VccD) and the spark is applied to another IO (on VccA), where does the energy go? Sorry if this basic question, but I want to understand why I need to do these rules.

Title: Re: Understanding ESD discharge
Post by thechopper on Jun 6^th, 2008, 8:32pm

The basic idea behind the ESD protection structures is to eat the current the ESD event generates in such a way that any other device the structure is protecting is prevented from conducting such current.
Currents during ESD events might get very large and as such, the protection devices need to have a very low dynamic resistance and be able to stand such current density.

Regards
Tosei

Title: Re: Understanding ESD discharge
Post by rajeee1000 on Jun 8^th, 2008, 10:24pm

Please read the following paper for grasping a few facts about ESD protection:

Ker, M.-D., "Whole-chip ESD protection design with efficient VDD-to-VSS ESD clamp circuit for submicron CMOS VLSI." IEEE Trans. on Electron Devices

Rajesh