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Design >> Analog Design >> want suggestion on low delay comparator design
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Message started by manodipan on Jun 9^th, 2008, 9:06am

Title: want suggestion on low delay comparator design
Post by manodipan on Jun 9^th, 2008, 9:06am

Hi Guys,
I am facing some problem in comparator design.I want a (1-2)ns and low slew(<300ps) comparator.For that purpose i have designed one cascaded differential amplifier(first 3 stages) connected to a level converter and then final inverter.Supply is 1.2V and 0.13um process.The delay and slew i get for this is 3.2 ns and very large slew(~1ns).Each differential amplifier consumes around 20uA.So can u suggest some better solution for my design.Does a preamplifier help in this case??pls reply soon...

Title: Re: want suggestion on low delay comparator design
Post by Berti on Jun 9^th, 2008, 10:11pm

What do you mean with "slew"?

Title: Re: want suggestion on low delay comparator design
Post by manodipan on Jun 9^th, 2008, 11:07pm

Here slew means the output changesfrom logic lo to hi or hi to lo in that time .So essentially output takes that much time to change from one logic to other..traditionally it os defined as time to reach from 10% to 90% of the signal.

Title: Re: want suggestion on low delay comparator design
Post by jiesteve on Jun 10^th, 2008, 12:03am

You want to have enough bias current to meet your slew rate requirement. Use minimum or near minimum length and use a low gain topology...

Title: Re: want suggestion on low delay comparator design
Post by manodipan on Jun 10^th, 2008, 10:40pm

Hi Jiesteve,
Lot of thanks for ur help,my circuit has worked.But i have some questions:i have used minimum length devices,and for low gain topology i have used higher overdrive devices(Vdsat),so it increases the current without changing the size,thus improve the speed.But menwhile the power is consumed ,how to minimise the power consumption in this case??

Title: Re: want suggestion on low delay comparator design
Post by jiesteve on Jun 11^th, 2008, 9:48pm

It's hard to tell you without looking at your circuit. Assuming your load is fixed and you have enough bias current flowing to meet your slew rate requirement then to save power you generally need to make device sizes smaller, at the cost of increased mismatch (offset), reduced swing and what not...