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https://designers-guide.org/forum/YaBB.pl Design >> Analog Design >> someone has designed BJT anolog IC? https://designers-guide.org/forum/YaBB.pl?num=1213281110 Message started by arlo on Jun 12th, 2008, 7:31am |
Title: someone has designed BJT anolog IC? Post by arlo on Jun 12th, 2008, 7:31am hi: There is one question. We can only use the fixed-size model in the design of BJT ic ? Or we can zoom in (zoom out) the emitter area of the model which is provided by foundry?And whether it will affect the precision of simulation? Because i know if the width or length of the mos exceed the limition of the model , the result of the simulation will be inaccurate. Thanks. |
Title: Re: someone has designed BJT anolog IC? Post by wowbigwolf on Jun 12th, 2008, 7:44am thinking... |
Title: Re: someone has designed BJT anolog IC? Post by ACWWong on Jun 12th, 2008, 2:38pm BJT models generally scale well with emitter area, unlike BSIM type modelling of MOS beyond the fitting limits for W & L as you suggest. What model are you using ? Gummel-Poon ? What device is it ? parasitic pnp in a MOS technology or properly constructed npn ? If you want to sure and only have a model for a fixed BJT size, then simply use iterated instances to increase the emitter area. |
Title: Re: someone has designed BJT anolog IC? Post by sheldon on Jun 12th, 2008, 7:33pm Arlo, The question is complex. The SPICE Gummel-Poon model does not scale well because the scaling assumptions are primitive. The scaling basically assumes a fixed emitter length with no modeling of end effects. In addition, the model has no capability for distinguishing between bipolar transistor structures, for example, modeling the effect of double base contacts on base resistance. I think that some of the more modern models do provide this capability, HiCUM(?). In practice, I have seen both scalable and fixed geometry based bipolar models. For scalable Gummel-Poon modeling, the model parameters are defined as functions of geometry. This actually works very well and can be combined with statsitical modeling, that is, scalable bipolar models with statistical dependency. See the Spectre Monte Carlo modeling application note for some discussion of how to include geometric dependency in models. The only problem with this approach is finding someone who is willing to do the modeling! On the other hand, using fixed models is a simple and robust methodology that the fab tends to prefer. These comments apply to vertical devices. I don't think that scaling of lateral devices is appropriate other than using multiple devices. Also, AC is correct about modeling, it is better to use scale factor rather than scaling emitter area if you are interested in model accuracy, however, you will pay a price in performance. For the effect of parasitics tends scale down as the device scales up so 10x larger device will have better speed-power performance than 10 1x devices. Best Regards, Sheldon |
Title: Re: someone has designed BJT anolog IC? Post by arlo on Jun 13th, 2008, 8:16am Thanks to ACWWong and Sheldon. I think i have gotten much. :) Especially, Sheldon you are so nice to explain the question in detail. To ACWWong: I use the G-P model of CHARTERED SEMICONDUCTOR MANUFACTURING LTD.It is a 0.6um BiCMOS process based bipolar.So,what is the different between ‘parasitic pnp in a MOS technology or properly constructed npn ’ ? To Sheldon: What is 'AC is correct about modeling'? And how can i 'use scale factor ' ? Because i don't know more other than changing the size of emitter. |
Title: Re: someone has designed BJT anolog IC? Post by sheldon on Jun 13th, 2008, 9:06am Arlo, AC is saying that there are two options for scaling the transistor: 1) Scale the device by stretching the emitter width to create a larger device or 2) Make many copies of the device and connect them in parallel Use option 1 and the accuracy of the model will be degraded, use option 2 and the accuracy will be good but the parasitics will be larger. Technically there is a third option, you could stretch the base and collector and make multiple copies of the emitter. This is slightly more accurate than 1 and has less parasitics than 2. See the attachment for pictures. Best Regards, Sheldon |
Title: Re: someone has designed BJT anolog IC? Post by arlo on Jun 14th, 2008, 5:45am sheldon, I think i have known what you said. It's a wonderful way.So it looks like the Question is solved. Thanks very much. But would you like answer me another Q ? Now , the most of IC has been produced by CMOS process including analog chip, so i don't know how far the BiCMOS or bipolar process can go. In other word, what can i do in analog domain if i put me into BiCMOS or bipolar? RF? Power? |
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